AN4506 datasheet(45/47 Pages) STMICROELECTRONICS

45 / 47 page

AN4506

First-in first-out (FIFO) buffer

DocID026442 Rev 2

45/47

6.5

Retrieving data from FIFO

When FIFO is enabled and the mode is different from Bypass, reading output registers (28h

to 2Dh) returns the oldest FIFO sample set.

Whenever output registers are read, their content is moved to the SPI/I2C output buffer.

FIFO slots are ideally shifted up one level in order to create room for receiving new samples

and the output registers load the current oldest value stored in the FIFO buffer.

The entire FIFO content is retrieved by performing 32 read operations from the gyroscope

output registers, every other read operation returns the same last value until a new sample

set is available in the FIFO buffer.

Data can be retrieved from FIFO using every read byte combination in order to increase

application flexibility (ex: 196 single byte reads, 32 reads of 6 bytes, 1 multiple read of 196

bytes, etc.).

It is recommended to read all FIFO slots in a multiple byte read of 196 bytes (6 output

registers by 32 slots) faster than 1*ODR. In order to minimize communication between

master and slave the read address is automatically updated by the device; it rolls back to

0x28 when register 0x2D is reached.

In order to avoid losing data, the right ODR must be selected according to the serial

communication rate available. In the case of standard I2C mode being used (max. rate

100 kHz), a single sample set reading takes 830 μs while total FIFO download is about

17.57 ms. I2C speed is slower than SPI and it needs about 29 clock pulses to start

communication (start, slave address, device address+write, restart, device address+read)

plus an additional 9 clock pulses for every byte to read. If this recommendation were

followed, the complete FIFO reading would be performed faster than 1*ODR; this means

that using a standard I2C, the selectable ODR must be lower than 57 Hz. If a fast I2C mode

is used (max. rate 400 kHz), the selectable ODR must be lower than 228 Hz.

Figure 29. FIFO reading diagram - FTH[4:0] = 10

In Figure 29 “Rx” indicates a 6-byte reading operation and “F0*” represents a single ODR

slot expanded in the diagram.

AN4506 Datasheet(PDF) 45 Page - STMicroelectronics