AN4506 datasheet(44/47 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN4506

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After the interrupt occurs and FIFO switches to FIFO mode, the buffer starts collecting data

and fills all the 32 slots (from F0 to F31) at the selected output data rate. When the buffer is

full, the OVRN bit goes up and data collection is permanently stopped; the user can read

FIFO content. The reading procedure is composed of a 32 sample set of 6 bytes for a total

of 192 bytes and retrieves data starting from the oldest sample stored in FIFO (F0). The

OVRN bit is reset when the first sample set has been read.

6.4

FIFO threshold

FIFO threshold is a configurable flag that can be used to generate a specific interrupt in

order to know when the FIFO buffer contains at least the number of samples defined as the

threshold level. The user can select the desired level in a range from 0 to 31 using the

FSS[4:0] field in the FIFO control register while the FIFO source register FSS[4:0] always

contains the number of samples stored in FIFO. If FSS[4:0] is greater than FTH[4:0], the

FTH bit is set high in the FIFO source register; on the contrary, FTH is driven low when the

FSS[4:0] field becomes lower than FTH[4:0]. FSS[4:0] increases by one step at the ODR

frequency and decreases by one step every time that a sample set reading is performed by

the user.

Figure 28. FIFO threshold behavior - FTH[4:0] = 10

In Figure 28, the first row indicates the FSS[4:0] value, the second row indicates the relative

FIFO slot and the last row shows the incremental FIFO data. Assuming FSS[4:0] = 10, the

FTH flag changes from “0” to “1” when the eleventh FIFO slot is filled (F10). Figure 29

shows that the FTH flag goes low when the FIFO content is less than FTH[4:0] which means

that nine unread sample sets remain in FIFO.

The FIFO threshold flag (FTH) can be enabled to generate a dedicated interrupt on the

DRDY/INT2 pin by setting the INT2_FTH bit high in the CTRL3 register.

AN4506 Datasheet(PDF) 44 Page - STMicroelectronics