AN3114 datasheet(19/43 Pages) STMICROELECTRONICS

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AN3114

Integrated LCD controller

Doc ID 16829 Rev 3

19/43

Figure 11.

Medium+ and high density LCD controller block diagram

3.1.1

Frequency generator block

The first block of the LCD controller is the frequency generator. It consists of a 16-bit ripple

counter prescaler and a programmable clock divider with a divider factor ranging from 16 to

31. It generates the LCD frequency, ck_div, starting from the input clock frequency, fLCDCLK.

The 16-bit prescaler divides fLCDCLK by 1 up to 65536. The value can be configured through

the PS[3:0] bits in the LCD_FRQ register. If a finer resolution rate is required, a second

divider can be used to further divide fck_ps by a factor of 16 to 31. This second factor is

configured through the DIV[3:0] bits in the LCD_FRQ register. fck_div is given by the

following equation:

LCDCLK

LCD RAM

(44x8 bits)

COM0

COM7

SEG43

SEG0

VLCD

VSS

SEG[43:0]

COM[7:0]

PS[3:0]

DIV[3:0]

LCDCLK/65536

LCDCLK

ck_div

CLOCK MUX

Divide by 16 to 31

Analog

switch

array

CONTRAST

CONTROLLER

LCD REGS

VOLTAGE

GENERATOR

CC[2:0]

1/3-1/4 VLCD

2/3 -3/4VLCD

1/2 VLCD

COM

DRIVER

SEG

DRIVER

BIAS[1:0]

Interrupt

PULSE GEN

ck_ps

I/O Ports

Analog booste r

READY

VSEL

STATIC

16-bit Prescaler

LCD REGS

FREQUENCY GENERATOR

COMMON/SEGMENT DRIVER

CONTRAST CONTROLLER

ck_div

CLKLCD

DIV

()

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