AN3114 datasheet(20/43 Pages) STMICROELECTRONICS

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Integrated LCD controller

AN3114

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Doc ID 16829 Rev 3

fframe is the operating frequency. It should be evaluated by taking into account the operating

frequency of the LCD device used in application. This range is typically from 30 to 100 Hz. It

is a compromise between power consumption and an acceptable refresh rate.

To generate fframe in the LCD operating frequency range using the prescaler and the divider,

the LCDCLK input clock must be in the range of 16.384 KHz to 500 KHz. For more details,

refer to section Clock control of the reference manual (RM0031). fframeis given by the

following equation:

where the duty can be static, 1/2, 1/3, 1/4 or 1/8.

3.1.2

Common/segments drive block

The second block of the LCD controller is the common/segments drive. It contains the timing

circuitry which allows to generate the appropriate waveforms to drive the common and the

segments lines. Refer to the reference manual RM0031 (section 17.3.3 Common driver) for

additional details.

This block also contains the LCD_RAM registers which bits correspond to the individual

pixels to be displayed on the LCD device.

In addition to the common/segments drive block features, a blink prescaler allows to select

the blink frequency. This frequency is defined by setting the BLINKF[2:0] bits of the

LCD_CR1 register from 0 to 7. Refer to the reference manual RM0031 (section 17.3.2

Frequency generator) for additional details.

3.1.3

LCD contrast controller block

The last block is the contrast controller. It plays a key role in the LCD controller since it

allows to adjust the contrast to the optimal value depending on the trade-off between the

power consumption and a satisfactory contrast level for the application.

The contrast depends on the VLCD voltage level which either internally generated by the

booster or externally provided on the Vlcd pin.

External VLCD voltage source

The external VLCD voltage source is selected by setting the VSEL bit to ‘1’ in the LCD_CR2

varying the dead time (up to seven phase periods) between each couple of frames where

the COM and SEG values are low simultaneously.

Internal VLCD voltage source

The internal booster is selected by clearing the VSEL bit in LCD_CR2. In this case, the

contrast is controlled by adjusting VLCD by software. In medium density STM8L152xx, and

STM8AL3Lxx devices, the adjustment is from 2.6 to 3.3 V. In medium+ and high density

STM8L152xx and STM8L162xx devices, the eight-step adjustment is from 2.6 to 3.5 V.

Please refer to the product datasheets.

frame

ck_div

duty

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