UM0842 datasheet(10/50 Pages) STMICROELECTRONICS

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Configuration

UM0842

10/50

Doc ID 16542 Rev 4

Configuration

5.1

Ethernet

There are two Ethernet PHYs (U5 and U6) available on the board that are connected

through the media independent interfaces (MII) to the Ethernet MACs on the CPU board

processor.

By default the MII addresses of the Ethernet PHYs are selected as shown in Table 1.

)

By default the initial configuration of the Ethernet PHYs is selected as shown in Table 2.

There are two LEDs embedded in each RJ-45 connector (CN7 and CN8) that indicate the

status of the line:

The green LED in the connector is driven on continuously when the Ethernet link is

established with the counterpart.

The yellow LED in the connector blinks when there is TX or RX activity.

The Serial Management Interface (SMI) is part of the MII interface and is used to transfer

management information between the MAC and PHY (access of the PHY registers). There

are two SMI interfaces coming from each Ethernet MAC. It is possible to use only one of

them to control both Ethernet PHYs or each SMI can be used separately for each PHY.

Table 1.

MII addresses of the Ethernet PHYs (U5 and U6)

Ethernet PHY

MII address

0x01

0x02

Table 2.

Default configuration of the Ethernet PHYs (U5 and U6)

Function

Default configuration

Auto negotiation

Enabled

10/100 Mbits

100 Mbits selected for auto negotiation advertisement

Half/Full duplex

Full duplex selected for auto negotiation advertisement

Internal Loopback

Disabled

Power down

Disabled (PHY is not in Power down state)

MII/RMII mode

MII selected

Table 3.

SMI interface configuration

Function

Default configuration

MII1_MDC, MII1_MDIO used for PHY1 (U5) and

MII2_MDC, MII2_MDIO used for PHY2 (U6)

R93,R94, R95, R96 loaded

R27, R29 not loaded (Default)

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