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UPD75P4308GS Datasheet(PDF) 25 Page - NEC |
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UPD75P4308GS Datasheet(HTML) 25 Page - NEC |
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25 / 60 page ![]() µPD75P4308 25 Group Mnemonic Operand No. of Machine Operation Addressing Skip condition bytes cycle area Branch BRNote1 addr — — PC12 - 0 ← addr *6 Assembler selects the most appropriate instruction among the following: • BR !addr • BRCB !caddr • BR $addr addr1 — — PC12 - 0 ← addr1 *11 Assembler selects the most appropriate instruction among the following: • BRA !addr1 • BR !addr • BRCB !caddr • BR $addr1 !addr 3 3 PC12 - 0 ← addr *6 $addr 1 2 PC12 - 0 ← addr *7 $addr1 1 2 PC12 - 0 ← addr1 PCDE 2 3 PC12 - 0 ← PC12 - 8 + DE PCXA 2 3 PC12 - 0 ← PC12 - 8 + XA BCDE 2 3 PC12 - 0 ← BCDENote 2 *6 BCXA 2 3 PC12 - 0 ← BCXANote 2 *6 BRANote 1 !addr1 3 3 PC12 - 0 ← addr1 *11 BRCB !caddr 2 2 PC12 - 0 ← PC12 + caddr11 - 0 *8 Notes 1. Shaded areas indicate support for the Mk II mode only. 2. Only the lower 2 bit in the B register is valid. |
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