W97AH6KB datasheet(4/127 Pages) WINBOND

4 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 4 -

8.2.5

AC and DC Output Measurement Levels ..................................................................................................................... 88

8.2.5.1

Single Ended AC and DC Output Levels ........................................................................................................... 88

8.2.5.2

Differential AC and DC Output Levels ............................................................................................................... 88

8.2.5.3

Single Ended Output Slew Rate........................................................................................................................ 88

8.2.5.4

Differential Output Slew Rate ............................................................................................................................ 90

8.2.5.5

Overshoot and Undershoot Specifications ........................................................................................................ 91

8.2.6

Output buffer Characteristics ....................................................................................................................................... 92

8.2.6.1

HSUL_12 Driver Output Timing Reference Load............................................................................................... 92

8.2.6.2

RONPU and RONPD Resistor Definition .............................................................................................................. 92

8.2.6.3

RONPU and RONPD Characteristics with ZQ Calibration..................................................................................... 93

8.2.6.4

Output Driver Temperature and Voltage Sensitivity........................................................................................... 93

8.2.6.5

RONPU and RONPD Characteristics without ZQ Calibration................................................................................ 94

8.2.6.6

RZQ I-V Curve .................................................................................................................................................. 95

8.2.6.7

Input/Output Capacitance ................................................................................................................................. 97

8.3

IDD Specification Parameters and Test Conditions ..................................................................................................... 98

8.3.1

IDD Measurement Conditions...................................................................................................................................... 98

8.3.1.1

Definition of Switching for CA Input Signals ...................................................................................................... 98

8.3.1.2

Definition of Switching for IDD4R ...................................................................................................................... 99

8.3.1.3

Definition of Switching for IDD4W ..................................................................................................................... 99

8.3.2

IDD Specifications ..................................................................................................................................................... 100

8.3.2.1

LPDDR2 IDD Specification Parameters and Operating Conditions, -40°C~85°C (x16, x32) ............................ 100

8.3.2.2

IDD6 Partial Array Self-Refresh Current, -40°C~85°C (x16, x32) .................................................................... 102

8.4

Clock Specification..................................................................................................................................................... 102

8.4.1

Definition for tCK(avg) and nCK................................................................................................................................. 102

8.4.2

Definition for tCK(abs) ............................................................................................................................................... 102

8.4.3

Definition for tCH(avg) and tCL(avg).......................................................................................................................... 103

8.4.4

Definition for tJIT(per)................................................................................................................................................ 103

8.4.5

Definition for tJIT(cc) ................................................................................................................................................. 103

8.4.6

Definition for tERR(nper) ........................................................................................................................................... 103

8.4.7

Definition for duty Dycle Jitter tJIT(duty) .................................................................................................................... 104

8.4.8

Definition for tCK(abs), tCH(abs) and tCL(abs) .......................................................................................................... 104

8.5

Period Clock Jitter...................................................................................................................................................... 104

8.5.1

Clock Period Jitter Effects on Core Timing Parameters ............................................................................................. 104

8.5.1.1

Cycle Time De-rating for Core Timing Parameters .......................................................................................... 104

8.5.1.2

Clock Cycle De-rating for Core Timing Parameters ......................................................................................... 105

8.5.2

Clock Jitter Effects on Command/Address Timing Parameters .................................................................................. 105

8.5.3

Clock Jitter Effects on Read tTiming Parameters....................................................................................................... 105

8.5.3.1

tRPRE ............................................................................................................................................................ 105

8.5.3.2

tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) ......................................................................................... 105

8.5.3.3

tQSH, tQSL..................................................................................................................................................... 105

8.5.3.4

tRPST............................................................................................................................................................. 106

8.5.4

Clock Jitter Effects on Write Timing Parameters ........................................................................................................ 106

8.5.4.1

tDS, tDH ......................................................................................................................................................... 106

8.5.4.2

tDSS, tDSH..................................................................................................................................................... 106

8.5.4.3

tDQSS ............................................................................................................................................................ 106

8.6

Refresh Requirements ............................................................................................................................................... 107

8.6.1

Refresh Requirement Parameters ............................................................................................................................. 107

8.7

AC Timings ................................................................................................................................................................ 108

8.7.1

LPDDR2 AC Timing .................................................................................................................................................. 108

8.7.2

CA and CS_n Setup, Hold and Derating .................................................................................................................... 113

8.7.2.1

CA and CS_n Setup and Hold Base-Values for 1V/nS .................................................................................... 113

8.7.2.2

Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220 ................................................................................ 114

8.7.2.3

Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition......................................................... 114

8.7.2.4

Nominal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock.............................. 115

8.7.2.5

Nominal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock................................................ 116

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