W97AH6KB datasheet(92/127 Pages) WINBOND

92 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 92 -

8.2.6

Output buffer Characteristics

8.2.6.1

HSUL_12 Driver Output Timing Reference Load

These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment

or a depiction of the actual load presented by a production tester. System designers should use IBIS or other

simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

0.5 x VDDQ

Cload = 5pF

VREF

Output

LPDDR2

SDRAM

VTT = 0.5 x VDDQ

RTT = 50

Figure of HSUL_12 Driver Output Reference Load for Timing and Slew Rate

Note:

All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this

reference load. This reference load is also used to report slew rate.

8.2.6.2

RONPU and RONPD Resistor Definition

RONPU =

)

(

)

(

–

Iout

ABS

Vout

VDDQ

Note: This is under the condition that RONPD is turned off

RONPD =

)

(Iout

ABS

Vout

Note: This is under the condition that RONPU is turned off

Chip in Drive Mode

VDDQ

VSSQ

Output Driver

IPU

IPD

RONPU

RONPD

IOut

VOut

Other

Circuityrt

RCV,

...

Figure of Output Driver Definition of Voltages and Currents

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