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W97AH6KB Datasheet(PDF) 20 Page - Winbond |
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W97AH6KB Datasheet(HTML) 20 Page - Winbond |
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20 / 127 page  W97AH6KB / W97AH2KB Publication Release Date: May 15, 2014 Revision: A01-001 - 20 - 7.3.2 MR0_Device Information (MA[7:0] = 00H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) RZQI DNVI DI DAI DAI (Device Auto-Initialization Status) Read-only OP0 0b: DAI complete 1b: DAI still in progress DI (Device Information) Read-only OP1 0b: S4 SDRAM DNVI (Data Not Valid Information) Read-only OP2 0b: LPDDR2 SDRAM will not implement DNV functionalit RZQI (Built in Self Test for RZQ Information) Read-only OP[4:3] 00b: RZQ self test not executed. 01b: ZQ-pin may connect to VDDCA or float 10b: ZQ-pin may short to GND 11b: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDDCA or float nor short to GND) Notes: 1. RZQI will be set upon completion of the MRW ZQ Initialization Calibration command. 2. If ZQ is connected to VDDCA to set default calibration by user, OP[4:3] shall be read as 01. If user does not want to connect ZQ pin to VDDCA, but OP[4:3] is read as 01 or 10, it might indicate a ZQ-pin assembly error. It is recommended that the assembly error being corrected first. 3. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 as defined above), the LPDDR2 device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. 4. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e., 240 Ohm ± 1%). 5. If the ZQ resistor is absent from the system, ZQ shall be connected to VDDCA. In this case, the LPDDR2 device shall ignore ZQ calibration commands and the device will use the default calibration settings. 7.3.3 MR1_Device Feature 1 (MA[7:0] = 01H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 nWR (for AP) WC BT BL BL Write-only OP[2:0] 010b: BL4 (default) 011b: BL8 100b: BL16 All others: reserved BT Write-only OP3 0b: Sequential (default) 1b: Interleaved WC Write-only OP4 0b: Wrap (default) 1 b: No wrap (allowed for SDRAM BL4 only) nWR Write-only OP[7:5] 001b: nWR=3 (default) 010b: nWR=4 011b: nWR=5 100b: nWR=6 101b: nWR=7 110b: nWR=8 All others: reserved 1 Note: 1. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). |
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