W97AH6KB datasheet(28/127 Pages) WINBOND

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W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 28 -

7.4.1.4

CKE Input Setup and Hold Timing

HIGH or LOW (but a defined logic level)

Tx+1

CK_t / CK_c

CKE

tISCKE

tIHCKE

VIHCKE

VILCKE

VIHCKE

VILCKE

Notes:

After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width).

After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width).

7.4.2

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW,

CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine

whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW).

The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst

read or write operation on successive clock cycles.

A new burst access must not interrupt the previous 4-bit burst operation in case of BL = 4 setting. In case of BL = 8

and BL = 16 settings, Reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this

occurs on even clock cycles after the Read or Write command and tCCD is met.

7.4.3

Burst Read Command

The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge

of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address

for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is

issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available RL

* tCK + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output

is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first

rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe.

The RL is programmed in the mode registers.

Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c.

W97AH6KB Datasheet(PDF) 28 Page - Winbond