W97AH6KB datasheet(70/127 Pages) WINBOND

70 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 70 -

7.4.25.11 Mode Register Read to Power-Down Entry

Tx+1

Tx+2

Tx+9

Tx+3

Tx+4

Tx+5

Tx+6

Tx+7

Tx+8

tISCKE

MRR

Mode Register Read operation starts with a MRR command and

CKE should be kept HIGH until the end of burst operation.

CK_c

CK_t

DQS_t

DQS_c

[Cmd]

CKE

Note:

CKE may be registered LOW RL + RU(tDQSCK(MAX)/tCK)+ BL/2 + 1 clock cycles after the clock on which the Mode Register Read command is

registered.

7.4.25.12 MRW Command to Power-Down Entry

T10

T11

MRW

tISCKE

CKE can go to LOW tMRW after a Mode Register Write command

CKE

[Cmd]

tMRW

CK_c

CK_t

Note:

CKE may be registered LOW tMRW after the clock on which the Mode Register Write command is registered.

7.4.26 Deep Power-Down

Deep Power-Down is entered when CKE is registered LOW with CS_n LOW, CA0 HIGH, CA1 HIGH, and CA2 LOW

at the rising edge of clock. A NOP command must be driven in the clock cycle following the power-down command.

CKE is not allowed to go LOW while mode register, read, or write operations are in progress. All banks must be in

idle state with no activity on the data bus prior to entering the Deep Power Down mode. During Deep Power-Down,

CKE must be held LOW.

In Deep Power-Down mode, all input buffers except CKE, all output buffers, and the power supply to internal circuitry

may be disabled within the SDRAM. All power supplies must be within specified limits prior to exiting Deep Power-

Down. VrefDQ and VrefCA may be at any level within minimum and maximum levels (See 8.1

“Absolute Maximum

DC Ratings

”). However prior to exiting Deep Power-Down, Vref must be within specified limits (See 8.2.1.1

“Recommended DC Operating Conditions”).

W97AH6KB Datasheet(PDF) 70 Page - Winbond

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