W97AH6KB datasheet(86/127 Pages) WINBOND

86 / 127 page

W97AH6KB / W97AH2KB

Publication Release Date: May 15, 2014

Revision: A01-001

- 86 -

Note that while CA and DQ signal requirements are with respect to Vref, the single-ended components of differential

signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_c and VDDCA/2 for CK_t, CK_c; this is nominally

the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

ended components of differential signals the requirement to reach VSEL(ac)max, VSEH(ac)min has no bearing on

timing, but adds a restriction on the common mode characteristics of these signals.

The signal ended requirements for CK_t, CK_c, DQS_t and DQS_c are found in 8.2.4.1.1

“Single-Ended AC and

DC Input Levels for CA and CS_n Inputs

” table and 8.2.4.1.3 “Single-Ended AC and DC Input Levels for DQ

and DM

” table, respectively.

Table of Single-Ended Levels for CK_t, DQS_t, CK_c, DQS_c

Symbol

Parameter

LPDDR2-800/1066

Unit

Notes

Min

Max

VSEH(AC)

Single-ended high-level for strobes

(VDDQ/2) + 0.220

Note 3

1, 2

Single-ended high-level for CK_t, CK_c

(VDDCA/2) + 0.220

Note 3

1, 2

VSEL(AC)

Single-ended low-level for strobes

Note 3

(VDDQ/2) - 0.220

1, 2

Single-ended low-level for CK_t, CK_c

Note 3

(VDDCA/2) - 0.220

1, 2

Notes:

1. For CK_t, CK_c use VSEH/VSEL(ac) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use

VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VSEH(ac)/VSEL(ac) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for

a signal group, then the reduced level applies also here.

3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c,

DQS3_t, DQS3_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for

overshoot and undershoot. Refer to section 8.2.5.5

“Overshoot and Undershoot Specifications”.

8.2.4.6

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each

cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements of

above Single-ended levels for CK_t, DQS_t, CK_c, DQS_c table. The differential input cross point voltage VIX is

measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

VDDCA/2 or VDDQ/2

VSSCA or VSSQ

VDDCA or VDDQ

CK_c, DQS_c

CK_t, DQS_t

VIX

Figure of Vix Definition

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