SAFC504 datasheet(39/71 Pages) INFINEON

39 / 71 page

C504

Data Sheet

2000-05

Figure 19

Block Diagram of the Oscillator Watchdog

Power Saving Modes

The C504 provides two power saving modes, the idle mode and the power down mode.

– In the idle mode, the oscillator of the C504 continues to run, but the CPU is gated

off from the clock signal. However, the interrupt system, the serial port, the A/D

Converter, and all timers with the exception of the Watchdog Timer, are further

provided with the clock. The CPU status is preserved in its entirety: the stack

pointer, program counter, program status word, accumulator, and all other registers

maintain their data during idle mode.

– In the power down mode, the RC oscillator and the on-chip oscillator which

operates with the XTAL pins are both stopped. Therefore all functions of the

microcontroller are stopped and only the contents of the on-chip RAM, XRAM and

the SFRs are maintained. The port pins, which are controlled by their port latches,

output the values that are held by their SFRs.

Table 10 gives a general overview of the entry and exit procedures of the power saving

modes.

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