SAFC504 datasheet(12/71 Pages) INFINEON

12 / 71 page

C504

Data Sheet

2000-05

PSEN

The Program Store Enable

output is a control signal that enables the external

program memory to the bus during external fetch

operations. It is activated every six oscillator periods

except during external data memory accesses.

Remains high during internal program execution.

ALE

The Address Latch Enable

output is used for latching the low-byte of the

address into external memory during normal

operation. It is activated every six oscillator periods

except during an external data memory access.

When instructions are executed from internal ROM

(EA = 1) the ALE generation can be disabled by

clearing bit EALE in SFR SYSCON.

COUT3

10-Bit compare channel output

This pin is used for the output signal of the 10-bit

Compare Timer 2 unit. COUT3 can be disabled and

set to a high or low state.

External Access Enable

When held at high level, instructions are fetched

from the internal ROM (C504-2R only) when the PC

is less than 4000H. When held at low level, the C504

fetches all instructions from external program

memory.

For the C504-L, this pin must be tied low.

P0.0 - P0.7 37 - 30

I/O

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0

pins that have “1”s written to them float; and in that

state, can be used as high-impedance inputs. Port 0

is also the multiplexed low-order address and data

bus during accesses to external program or data

memory. In this application, it uses strong internal

pullup resistors when issuing “1” s.

Port 0 also outputs the code bytes during program

verification in the C504-2R. External pullup resistors

are required during program (ROM) verification.

AREF

–

Reference voltage for the A/D converter.

Table 1

Pin Definitions and Functions (cont’d)

Symbol

Pin Number

(P-MQFP-44)

I/O

Function

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