SAFC504 datasheet(54/71 Pages) INFINEON

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C504

Data Sheet

2000-05

Further timing conditions:

ADC min = 500 ns

IN = 2/fOSC = 2 tCLCL

Notes:

AIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these

cases will be X000

H or X3FFH, respectively.

2) During the sample time, the input capacitance C

AIN can be charged/discharged by the external source. The

internal resistance of the analog source must allow the capacitance to reach their final voltage level within

After the end of the sample time

S, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time

S, the time for determining the digital result and the time for the

calibration. Values for the conversion clock

ADC depend on programming and can be taken from the table on

the previous page.

UE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other

voltages within the defined voltage range.

If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input

overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB

is permissible.

5) During the conversion, the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Clock Calculation Table

Clock Prescaler

Ratio

ADCL1, 0

ADC

ADCC

÷ 32

× t

384

× t

÷ 16

× t

192

× t

÷ 80

× t

÷ 40

× t

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