UT700 datasheet(29/46 Pages) AEROFLEX

29 / 46 page

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG

(VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55

oC to 105oC)

Notes:

1. All outputs are measured using the load conditions shown in Figure 17.

2. CB[7] is not tested in the case of BCH EDAC.

3. High-Z defined as +/-300mV change from steady state.

4. Guaranteed by design.

Symbol

Description

Min

Max

Units

t1a1

SDCLK

↑ to ADDR[27:0] valid

1.5

8.5

t1b1

SDCLK

↑ to SDCS[1:0] valid

7.5

t1c1

SDCLK

↑ to output valid

SDRAS, SDCAS, and SDWE

1.5

8.5

t1d1

SDCLK

↑ to SDDQM[3:0] valid

2.5

8.5

t1e1

SDCLK

↑ to output valid

(WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0],

RAMS[4:0], and READ)

t21,2

SDCLK

↑ to output valid

(DATA[31:0] and CB[15:0])

2.5

8.5

t31,2,3

SDCLK

↑ to output high-Z

(DATA[31:0] and CB[15:0])

2.5

8.5

t41

SDCLK

↑ to signal low

(ERROR and WDOG4)

t81,2,3

WRITE

↑ or RWE[3:0]↑ to output high-z

(DATA [31:0] and CB[15:0])

0.5

t91

Skew from first memory output signal transition to last memory output

signal transition

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