UT700 datasheet(3/46 Pages) AEROFLEX

3 / 46 page

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

2.0 Pin Identification and Description

Pin Function

Description

CMOS input

CMOS input Schmitt

CMOS output

I/O

CMOS bi-direct

CMOS open drain

PCI-I

PCI input

PCI-O

PCI output

PCI-I/O

PCI bi-direct

PCI-3

PCI three-state

2.1. System Signals

Notes:

1. This pin is actively driven low and must be tied to VDD through a pull-up resistor.

2.2 Address Bus

Pin Name

Function

Number

Reset

Value

Description

484 CLGA

SYSCLK

Y20

Main system clock

NODIV

E19

Clock divider input. Set to ‘1’ for 1x memory clock,

‘0’ for 1/2x memory clock, relative to SYSCLK.

RESET

L19

System reset

ERROR1

K19

Processor error mode indicator. This is an active low

output.

WDOG1

J19

Watchdog indicator. This is an active low output.

Pin Name

Direction

Number

Reset

Value

Description

484 CLGA

ADDR[0]

low

Bit 0 of the address bus

ADDR[1]

low

Bit 1 of the address bus

ADDR[2]

low

Bit 2 of the address bus

ADDR[3]

AA5

low

Bit 3 of the address bus

ADDR[4]

low

Bit 4 of the address bus

ADDR[5]

AB5

low

Bit 5 of the address bus

ADDR[6]

low

Bit 6 of the address bus

UT700 Datasheet(PDF) 3 Page - Aeroflex Circuit Technology

UT700 Datasheet(HTML) 3 Page - Aeroflex Circuit Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL