UT700 datasheet(34/46 Pages) AEROFLEX

34 / 46 page

36-00-00-000

Ver. 1.3.1

Aeroflex Microelectronics Solutions - HiRel

4.6 Timing Characteristics for PCI Interface

(VDD = 3.3V + 0.3V; VDDC = 1.2V + 0.1V; TC = -55

oC to 105oC)

Notes:

1. All outputs are measured using the load conditions shown in Figure 17.

2. High-Z defined as +/-300mV change from steady state.

3. PCI_TRDY, PCI_STOP, and PCI_DEVSEL timing is guaranteed by design when used as inputs.

4. PCI_PERR and PCI_GNT are guaranteed by design.

5. Guaranteed by design.

Symbol

Description

Min

Max

Units

t171

PCI_CLK

↑ to output valid

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME,

PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL,

PCI_PERR, PCI_REQ, and PCI_ARB_GNT[7:0])

213

t181,2

PCI_CLK

↑ to output valid from high-z

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME,

PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, and

PCI_PERR

213

t191,2

PCI_CLK

↑ to output high-Z

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME,

PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, and

PCI_PERR

t203,4

Setup time to PCI_CLK

↑

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME,

PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL,

PCI_PERR, PCI_IDSEL, PCI_GNT, and PCI_AR-

B_REQ[7:0])

4--

t213,4

Hold time from PCI_CLK

↑

(PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME,

PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL,

PCI_PERR, PCI_IDSEL, PCI_GNT, and PCI_AR-

B_REQ[7:0])

1--

t225

PCI_CLK

↑ to RESET deassertion

PCI Clocks

t23a5

PCI_CLK

↑ to PCI_RST deassertion

PCI Clocks

t23b5

PCI_RST assertion to PCI_CLK idle

PCI Clocks

t24

PCI_RST active to output high-Z

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