AD6674 datasheet(64/91 Pages) AD

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AD6674

Data Sheet

DDC 0

REAL/I

CONVERTER 0

CONVERTER 1

REAL/I

REAL/Q

DDC 1

REAL/I

CONVERTER 2

CONVERTER 3

REAL/I

REAL/Q

DDC 2

REAL/I

CONVERTER 4

CONVERTER 5

REAL/I

REAL/Q

DDC 3

REAL/I

CONVERTER 6

CONVERTER 7

REAL/I

REAL/Q

OUTPUT

INTERFACE

I/Q

CROSSBAR

MUX

ADC A

SAMPLING

REAL/I

ADC B

SAMPLING

REAL/Q

Figure 135. DDCs and Virtual Converter Mapping

JESD204B Tx CONVERTER MAPPING

To support the different chip operating modes, the AD6674

design treats each sample stream (real or I/Q) as originating

from separate virtual converters. The I/Q samples are always

mapped in pairs with the I samples mapped to the first virtual

converter, and the Q samples mapped to the second virtual

converter. With this transport layer mapping, the number of

virtual converters are the same whether a single real converter is

used along with a DDC block producing I/Q outputs, or an

analog downconversion is used with two real converters

producing I/Q outputs.

Figure 136 shows a block diagram of the two scenarios

described for I/Q transport layer mapping.

REAL

CONVERTER 0

CONVERTER 1

ADC

90°

PHASE

JESD204B

L LANES

I/Q ANALOG MIXING

M = 2

ADC

REAL

CONVERTER 0

CONVERTER 1

JESD204B

L LANES

DIGITAL DOWNCONVERSION

M = 2

DIGITAL

DOWN

CONVERSION

Figure 136. I/Q Transport Layer Mapping

The JESD204B Tx block for AD6674 supports up to four digital

DDC blocks. Each DDC block outputs either two sample streams

(I/Q) for the complex data components (real + imaginary) or

one sample stream for real (I) data. The JESD204B interface can

be configured to use up to eight virtual converters depending

on the DDC configuration. Figure 135 shows the virtual converters

and their relationship to DDC outputs when complex outputs

are used. Table 34 shows the virtual converter mapping for each

chip operating mode when channel swapping is disabled.

CONFIGURING THE JESD204B LINK

The AD6674 has one JESD204B link. It offers an easy way to

set up the JESD204B link through the quick configuration

SERDOUT3±) are considered to be part of one JESD204B link.

The basic parameters that determine the link setup are

•

Number of lanes per link (L)

•

Number of converters per link (M)

•

Number of octets per frame (F)

If the internal DDCs are used for on-chip digital processing,

the M value represents the number of virtual converters. The

virtual converter mapping setup is shown in Figure 135.

The maximum lane rate allowed by the JESD204B specification

is 12.5 Gbps. The lane rate is related to the JESD204B

parameters using the following equation:

Rate

Line

Lane

OUT 





















where:

Ratio

Decimation

CLOCK

ADC

OUT

The decimation ratio (DCM) is the parameter programmed in

Use the following steps to configure the output:

1. Power down the link.

2. Select the quick configuration options.

3. Configure detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

If the lane rate calculated is less than 6.25 Gbps, select the low

lane rate option by programming a value of 0x10 to Register 0x56E.

Rev. B | Page 64 of 91

AD6674 Datasheet(PDF) 64 Page - Analog Devices

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