 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD6674 Datasheet(PDF) 79 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD6674 Datasheet(HTML) 79 Page - Analog Devices |
|
|
79 / 91 page  Data Sheet AD6674 Reg. Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes 0x040 Chip pin control PDWN/STBY function 00 = power down 01 = standby 10 = disabled Fast Detect B (FD_B) 000 = Fast Detect B output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 111 = disabled Fast Detect A (FD_A) 000 = Fast Detect A output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 011 = temperature diode 111 = disabled 0x3F 0x10B Clock divider 0 0 0 0 0 000 = divide by 1 001 = divide by 2 011 = divide by 4 111 = divide by 8 0x00 0x10C Clock divider phase (local) 0 0 0 0 Independently controls Channel A and Channel B clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ½ input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed 0x00 0x10D Clock divider and SYSREF± control Clock divider auto- phase adjust 0 = disabled 1 = enabled 0 0 0 Clock divider negative skew window 00 = no negative skew 01 = 1 device clock of negative skew 10 = 2 device clocks of negative skew 11 = 3 device clocks of negative skew Clock divider positive skew window 00 = no positive skew 01 = 1 device clock of positive skew 10 = 2 device clocks of positive skew 11 = 3 device clocks of positive skew 0x00 Clock dvider must be >1 0x117 Clock delay control 0 0 0 0 0 0 0 clock fine delay adjustment enable 0 = disabled 1 = enabled 0x00 Enabling the clock fine delay adjust causes a datapath soft reset 0x118 Clock fine delay Clock Fine Delay Adjust[7:0] twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ≤−88 = −151.7 ps skew −87 = −150.0 ps skew … 0 = 0 ps skew … ≥ +87 = +150 ps skew 0x00 Used in conjunc- tion with Reg. 0x117 0x11C Clock status 0 0 0 0 0 0 0 0 = no input clock detected 1 = input clock detected 0x00 Read only 0x120 SYSREF± Control 1 0 SYSREF± flag reset 0 = normal operation 1 = flags held in reset 0 SYSREF± transition select 0 = low to high 1 = high to low CLK± edge select 0 = rising 1 = falling SYSREF± mode select 00 = disabled 01 = continuous 10 = N shot 0 0x00 0x121 SYSREF± Control 2 0 0 0 0 SYSREF± N shot ignore counter select 0000 = next SYSREF± only 0001 = ignore the first SYSREF± transitions 0010 = ignore the first two SYSREF± transitions … 1111 = ignore the first 16 SYSREF± transitions 0x00 Mode select (Reg. 0x120, Bits[2:1]) must be N shot Rev. B | Page 79 of 91 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
