AD6674 datasheet(76/91 Pages) AD

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AD6674

Data Sheet

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into seven sections: the

Analog Devices SPI registers, the analog input buffer control

registers, ADC function registers, the DDC function registers,

NSR decimate by 2 and noise shaping requantizer registers,

variable dynamic range registers, and the digital outputs and

test modes registers.

Table 45 (see the Memory Map Register Table section)

documents the default hexadecimal value for each hexadecimal

address shown. The column with the heading Bit 7 (MSB) is the

start of the default hexadecimal value given. For example,

Address 0x561, the output mode register, has a hexadecimal

default value of 0x01. This means that Bit 0 = 1, and the

remaining bits are 0s. This setting is the default output format

value, which is twos complement. For more information on this

function and others, see the Table 45.

Open and Reserved Locations

All address and bit locations that are not included in Table 45

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is open (for example, Address 0x561). If

the entire address location is open (for example, Address 0x013),

do not write to this address location.

Default Values

After the AD6674 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 45.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

•

“X” denotes a “don’t care”.

Channel Specific Registers

Some channel setup functions such as buffer input termination

(Register 0x016) can be programmed to a different value for

each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits are

designated in Table 45 as local. These local registers and bits can

be accessed by setting the appropriate Channel A or Channel B

bits in Register 0x008. If both bits are set, the subsequent write

affects the registers of both channels. In a read cycle, set only

Channel A or Channel B to read one of the two registers. If both

bits are set during an SPI read cycle, the device returns the value

for Channel A. Registers and bits designated as global in Table 45

affect the entire device and the channel features for which

independent settings are not allowed between channels. The

settings in Register 0x008 do not affect the global registers and

bits.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to Register 0x000,

the AD6674 requires 5 ms to recover. Therefore, when program-

ming the AD6674 for application setup, ensure that an adequate

delay is programmed into the firmware after asserting the soft

reset and before starting the device setup.

Rev. B | Page 76 of 91

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