TMS320C6472ECTZ datasheet(262/269 Pages) TI1

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TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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7.20.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan testing and emulation of the C6472 device. The

JTAG interface provides an asynchronous TRST and only the four primary JTAG signals (TCK, TDI, TMS,

and TDO) are required for boundary scan. The pins EMU0 and EMU1 have no effect on the operation of

the JTAG interface on the C6472 device. Most interfaces on the device follow the Boundary Scan Test

Specification (IEEE1149.1), while the SerDes (RapidIO) supports the AC coupled net test defined in AC

Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain

fashion, as per the specification.

7.20.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6472 DSP includes an internal pulldown (IPD) on the TRST pin to ensure

that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be

properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive

TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of

an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the

DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan

operations.

7.20.3.2 Boundary Scan Operation

The C6472 device supports boundary scan testing through the IEEE 1149.1 JTAG interface. The

TMS320C6472 BSDL Model (literature number SPRM384) is available to support boundary scan test

vector development. The BSDL model files list POR and RESET as compliance pins and define their

required state to be a 1. These pins must be pulled high prior to any boundary scan test sequence

initialization and they must remain steady at a high level throughout the boundary scan testing to attain

valid results. POR and RESET are the only pins (other than power and ground pins) that must remain at a

fixed state during the boundary scan testing.

The JTAG ID is commonly read by boundary scan test tools. Note that the VARIANT field in the JTAG ID

(see Section 3.10) may not be valid during boundary scan testing unless sufficient CLKIN1 clock cycles

have been received (see Section 7.7 and Figure 7-9).

In an ideal system designed for boundary scan test, all of the ICs would have their own JTAG interface

and all of the input and output pins would be controlled through the internal boundary scan cells. Since

many of the devices on boards, like clock buffers, do not contain boundary scan cells or a JTAG interface,

the outputs from these devices should be tristated during boundary scan testing. This allows all of the nets

attached to the C6472 device to be tested. Additionally, if testing is desired for SRIO, DDR, or RGMII pins

that may be powered down in some configurations, see the notes in Section 7.3.3. Additional BSDL files

are available for designs that have one or more of these three interfaces disabled.

262

C64x+ Peripheral Information and Electrical Specifications

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