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TMS320C6472ECTZ Datasheet(PDF) 263 Page - Texas Instruments

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Part # TMS320C6472ECTZ
Description  TMS320C6472 Fixed-Point Digital Signal Processor
PDF  269 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320C6472ECTZ Datasheet(HTML) 263 Page - Texas Instruments

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background image
2
1
3
4
TCLK
TDO
TDI/TMS
3
TCLK
EMUn
1
2
4
TMS320C6472
www.ti.com
SPRS612G
– JUNE 2009 – REVISED JULY 2011
7.20.3.3 JTAG Electrical Data/Timing
Table 7-155. Timing Requirements for JTAG
(see Figure 7-68)
500/625/700
NO.
UNIT
MIN
MAX
1
tc(TCLK)
Cycle time, TCLK
23.255
(1)
ns
3
tsu(TDIV-TCLKH)
Setup time, TDI/TMS/TRST valid before TCLK high
3
ns
4
th(TCLKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCLK high
6(2)
ns
(1)
Fully-synchronous design removes maximum clock period limitations.
(2)
Hold time measured from rising edge.
Table 7-156. Switching Characteristics Over Recommended Operating Conditions for JTAG
(see Figure 7-68)
500/625/700
NO.
UNIT
MIN
MAX
2
td(TCLKL-TDOV)
Delay time, TCLK low to TDO valid
0
12
ns
Figure 7-68. JTAG Timing
Table 7-157. Timing Requirements for HS-RTDX
(see Figure 7-69)
500/625/700
NO.
UNIT
MIN
MAX
1
tc(TCLK)
Cycle time, TCLK
10
20
ns
2
tsu(TCLKH-EMUn)
Setup time, EMUn input valid before TCLK high
1.5
ns
3
th(TCLKH-EMUn)
Hold time, EMUn input valid after TCLK high
3.0
ns
4
td(TCLKH-EMUn)
Delay time, TCLK high to EMUn output valid
3.0
tc(TCLK) - 3.5
ns
Figure 7-69. HS-RTDX Timing
Copyright
© 2009–2011, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications
263
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Product Folder Link(s) :TMS320C6472



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