TMS320C6472ECTZ datasheet(144/269 Pages) TI1

144 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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7.7.5

Module Reset

Module reset is initiated by LPSC and only resets the module controlled by that LPSC. To prevent stalls,

care must be taken when using this reset.

7.7.6

Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority

reset request. The rest request priorities are as follows (high to low):

•

Power-on Reset

•

Warm Reset

•

System Reset

•

Local Reset

7.7.7

Reset Controller Register

The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This

7.7.7.1

Reset Type Status Register Description

The rest type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur

simultaneously, this register latches the highest priority reset source. The reset type status register is

shown in Figure 7-8 and described in Table 7-13.

Reserved

R-0

Reserved

SRST

Rsvd

WRST

POR

R-0

R-x

R-0

R-x

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-8. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]

Table 7-13. Reset Type Status Register (RSTYPE) Field Descriptions

Bit

Field

Value

Description

31:4

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SRST

System reset.

System Reset was not the last reset to occur.

System Reset was the last reset to occur.

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

WRST

Warm reset.

Warm Reset was not the last reset to occur.

Warm Reset was the last reset to occur.

POR

Power-on reset.

Power-on Reset was not the last reset to occur.

Power-on Reset was the last reset to occur.

144

C64x+ Peripheral Information and Electrical Specifications

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