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TMS320C6472ECTZ Datasheet(PDF) 146 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 269 page ![]() CLKIN1 RESET RESETSTAT SYSREFCLK(PLL1C) ZGroup POR SYSCLK8 SYSCLK9 SYSCLK10 BootandDevice ConfigurationPins LowGroup HighGroup CLKIN2andCLKIN3 InternalResetPLL2C SYSREFCLK(PLL3C) SYSCLK7 1 5 3 4 Undefined Undefined Low High-Z Undefined High PLL3Unlocked PLL3Locked (A) Undefined Undefined PowerSuppliesRamping PowerSuppliesStable TMS320C6472 SPRS612G – JUNE 2009 – REVISED JULY 2011 www.ti.com A. SYSREFCLK of the PLL2 controller and PLL3 controller runs at CLKIN2 ×20 and CLKIN3 ×20, respectively. B. Power supplies, CLKIN1, CLKIN2 and CLKIN3 (if used) must be stable before the start of tw(POR). Figure 7-9. Power-Up Timing 146 C64x+ Peripheral Information and Electrical Specifications Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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