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TMS320C6472ECTZ Datasheet(PDF) 147 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 147 Page - Texas Instruments |
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147 / 269 page ![]() 1,2 3 4 PORRESET , BootPins RESETSTAT 5 POR RESET (A) RESETSTAT BootandDevice ConfigurationPins 2 5 3 4 TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 Table 7-14. Timing Requirements for Reset(1) (see Figure 7-10 and Figure 7-11) 500/625/700 NO. UNIT MIN MAX 20(2) 1 tw(POR) Width of the POR pulse μs 256D(3) 20(2) 2 tw(RST) Width of the RESET pulse μs 24C 3 tsu(boot) Setup time, boot configuration bits valid before POR or RESET high 12C ns 4 th(boot) Hold time, boot configuration bits valid after POR or RESET high 20 ns (1) P = 1/CPU clock frequency in nanoseconds (ns); C = 1/CLKIN1 clock frequency in ns; D = 1/CLKIN* clock frequency in ns, where * is the slowest of CLKIN1, CLKIN2, or CLKIN3. (2) No external pulls on GPIO. (3) With board assistance to reduce the RC time constant. Table 7-15. Switching Characteristics Over Recommended Operating Conditions for Reset (see Figure 7-10 and Figure 7-11) 500/625/700 NO. UNIT MIN MAX 5 td(PORH-RSTATH) Delay time, POR high and/or RESET high to RESETSTAT high 15000C ns Figure 7-10. Power-on Reset Timing A. RESET should only be used after device has been powered up. Figure 7-11. Warm Reset Timing Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 147 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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