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MCP2035 Datasheet(PDF) 57 Page - Microchip Technology |
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MCP2035 Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 68 page ![]() 2012 Microchip Technology Inc. DS22304A-page 57 MCP2035 TABLE 5-7: STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS) Condition Bit 8 (Note 2) Bit 7 (Note 2) Bit 6 Bit 5 Bit 4 (Note 2) Bit 3 (Note 2) Bit 2 Bit 1 Bit 0 CHZACT CHYACT Input (CHX) ACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI POR 0 00 0 0 00 0 1 Read Command (STATUS Register only) u uu u u uu 0 u Sleep Command u uu u u uu u u Soft Reset Executed (Note 1) 0 00 0 0 00 u u Legend: u = unchanged Note 1: See Section 5.19 “Soft Reset” and Section 5.30.2.4 “Soft Reset Command” for the condition of Soft Reset execution. 2: These bits have no meaning and are ignored in the MCP2035. TABLE 5-8: EXAMPLE OF SELECTING CONFIGURATION REGISTER BIT VALUES AND PARITY BITS Register Name Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Calculate d Row Parity Bit) Condition Config. Reg. 0 1 0 1 0 1 1 1 0 0 OEH = OEL = 2 ms, ALRTIND = 1, Input Channel (LCX) = Enabled Config Reg. 1 0 0 0 0 0 0 0 1 0 Output Data Type = Demodulated Output, Input Tuning Capacitor Value = 1 pF Config Reg. 2 0 0 0 0 0 0 0 0 1 RSSI Pull-Down MOSFET = Off, CLKDIV = 0 Config Reg. 3 0 0 0 0 0 0 0 0 1 Recommended Config Reg. 4 0 0 0 0 0 0 0 0 1 Input Channel Sensitivity Reduction = None Config Reg. 5 01 0 0 0 0 0 0 0 AGCSIG = 1, Min Modulation Depth = 33% Calculated Column Parity Register 6 0 0 01 00 0 0 0 Calculated Column Odd Parity Bits Note 1: The values in the colored area are strongly recommended for the best result. 2: See the calculated row and column parity bits. These bits must be programmed by the user. See Note in Section 5.30.3 “Read/Write Commands for Configuration Registers” for the parity bits. |
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