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MCP19124 Datasheet(PDF) 10 Page - Microchip Technology |
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MCP19124 Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 236 page  FIGURE 1-1: MCP19124/5 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM 5V to 10V VIN PDRV IP SDRV DESATN DESATP ISN ISP GPIO GPIO AGND PGND VDD VDD VDD VDR 4.7uF 4.7uF 10 Place recommended VDD and VDR 4.7 µF capacitors as close to respective pins as possible. VIN VDR VDD (5V) BGAP UVLO 8 8 BGAP PIC CORE OSC OV UVLO PDRV ISN I A = 10 IP LEB 2 EA_SC PWM Comp PWM Logic DESATN QRS VDR AGND MCLR DIMI SDA TEMP VS BIN I/O x 3 (x7 MCP19125) OV 6 CCD SDRV 4 4 EN1 EN2 OVLO 4 VCOMP PGND PGND PGND VDD GPB1 I/O LDO1 LDO2 Bias Gen AVDD (4V) AVDD VDD 8 DESAT MUX 4V to 20V 8.8V to 44V BGAP DESATP ISP VDD_OK Gate Drive Timing Gate Drive Timing IP_COMP A2 EA1 OVLO_REF UVLO_REF Interrupt and Logic to PWM & PIC 4 msb VIN_UVLO Log Lin Slope Comp ADJ Offset VIN_OVLO + - - + OVLO PWM BGAP BGAP BGAP VDR UVLO BGAP 2.7V or 5.4V ADC 4 msb 2 lsb 2 lsb BGAP BGAP EA2 OV EA1DIS EA2DIS EA2DIS EA1DIS VDD or AVDD REF VREF Lin OVREF Lin VREF Lin |
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