MCP19124 datasheet(20/236 Pages) MICROCHIP

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MCP19124/5

DS20005619A-page 20

 2016 Microchip Technology Inc.

stays low and TMR2 is allowed to run until the

PWM signal kicks off a new cycle.

The desaturation comparator module is controlled by

the DESATCON register.

3.6

Start-Up

To control the output current during start-up, the

MCP19124/5 have the capability to monotonically

increase system current, at the user’s discretion. This

is accomplished through the control of the reference

voltage DAC (VREF). Users also have firmware control

over the switching frequency through Timer2 and the

PR2 register. Maximum duty cycle control is

established through the PWMRL register. See section

Section 27.0 “Enhanced PWM Module” for details.

The entire start-up profile is under user control via

software.

3.7

Driver Control Circuitry

Internal to the driver control circuitry of the

MCP19124/5 are two error amplifiers (EA1/EA2). Both

error amplifiers are transconductance designs with

external compensation. This dual error amplifier

configuration allows the device to regulate current or

voltage. 8-bit DAC VREF is summed with the pedestal

voltage (VZC) and connected to the noninverting input

of the current regulating error amplifier (EA1) to create

the current regulation set-point. This is very similar to

the current regulation scheme utilized in the

MCP19114/5 devices.

In the MCP19124/5 devices, a second control loop

utilizing the voltage control error amplifier (EA2) can

implement voltage control regulation. The output of

each error amplifier is clamped to the other such that

the outputs are typically with 50mV. The control loop

(voltage or current) that is demanding the smaller error

amplifier output signal is in control of the PWM control

loop. The 8-bit OVREF DAC is connected to the

noninverting input of the voltage control error amplifier

(EA2) and sets the voltage command level. When EA2

is disabled via the EA2DIS bit in the ABECON register

the overvoltage comparator is enabled and functions

as overvoltage detection/protection similar to the

MCP19114/5 devices.

When current regulation is implemented, the error

amplifier (EA1) generates the control voltage used by

the high-speed PWM comparator. There is an internally

generated reference voltage, VREF. The difference or

error between this internal reference voltage and the

actual feedback voltage from the secondary current

sense output is the control voltage. When voltage

regulation is implemented, the error amplifier (EA2)

generates the control voltage used by the high-speed

PWM comparator. There is an internally generated

reference voltage, OVREF. The difference or error

between this internal reference voltage and the actual

feedback voltage present at the VS pin is the control

voltage. Independent external compensation networks

are connected at the ICOMP and VCOMP pins to allow

greater compensation flexibility for voltage and current

regulation stabilization of the control system.

Since the MCP19124/5 are peak current mode

controlled, the comparator compares the primary peak

current waveform (IP) that is based upon the current

flowing in the primary side with the error amplifier

control output voltage. This error amplifier control

output voltage also has user-programmable slope

compensation subtracted from it. In fixed-frequency

applications, the slope compensation signal is

generated to be greater than 1/2 the down slope of the

inductor current waveform and is controlled by the

SLPCRCON register. Offset adjust ability is also

available to set the peak current limit of the primary

switch for overcurrent protection. The range of the

slope compensation ramp is specified. When the

current sense signal reaches the level of the control

voltage minus slope compensation, the ON cycle is

terminated and the external PDRV switch is latched off

until the beginning of the next cycle which begins at the

next clock cycle.

To improve current regulation at low levels, a pedestal

voltage (VZC) set to the BG (1.23V) is implemented

throughout the current regulation analog control loop.

This virtual ground serves as the reference for the error

amplifier (EA1), slope compensation, current sense

amplifier (A2) and the IP offset adjustment.

An S-R latch (Set-Rest-Flip-Flop) is used to prevent the

PWM circuitry from turning the external switch on until

the beginning of the next clock cycle.

3.8

Fixed PWM Frequency

The switching frequency of the MCP19124/5, while not

controlled by the DESAT comparator output, is

generated by using a single edge of the 8 MHz internal

clock. The user sets the MCP19124/5 switching

frequency by configuring the PR2 register. The

maximum allowable PDRV duty cycle is adjustable and

controlled

the

PWMRL

The

programmable range of the switching frequency will be

31.25 kHz to 2 MHz. The available switching frequency

below 2 MHz is defined as FSW = 8 MHz/N, where N is

a whole number between 4

 N  256. Refer to

Section 27.0 “Enhanced PWM Module” for details.

3.9

VREF

This reference is used to generate the voltage

connected to the noninverting input of the current error

amplifier (EA1). The entire analog control loop is raised

to a virtual ground pedestal (VZC) equal to the

Band Gap voltage (1.23V).

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