LAN8742AI-CZ datasheet(119/124 Pages) MICROCHIP

119 / 124 page

 2013-2015 Microchip Technology Inc.

DS00001989A-page 119

LAN8742A/LAN8742Ai

APPENDIX A: REVISION HISTORY

REVISION LEVEL

& DATE

SECTION/FIGURE/ENTRY

CORRECTION

Revision A

(09-07-15)

Replaces the previous SMSC version Rev. 1.1

• Added Note and Trademark page

• Added Worldwide Sales and Services page

• Added Product Identification System

• Changed ‘QFN’ to ‘VQFN’

Chapter 2, "Pin Description and

Configuration"

• Figure 2-1: rotated 90° cw

• Table 2-3, “Serial Management Interface (SMI)

Pins”: Changed “VIS/VOD8 (PU)” to “VIS/VO8

(PU)”

Section 4.1, "Register Nomenclature"

Table 4-1, “Register Bit Types”, register bit

description for byte type notification ‘W’: Changed

“read” to ‘written”

Section 5.6.4, "RMII Interface Timing"

Updated RMII timing table: Updated REF_CLK In

mode toval max from “14.0 ns” to “15.0 ns”

Section 5.7, "Clock Circuit"

Added new 100 µW crystal specifications and circuit

diagram. The section is now split into two

subsections, one for 300 µW crystals and the other

for 100 µW crystals.

Chapter 6, "Package Outline"

Updated package outline drawing information

Rev. 1.1

(05-21-13)

General

• Changed part numbers from

“LAN8742/LAN8742i” to

“LAN8742A/LAN8742Ai”

• Updated ordering information

• Updated figures

Chapter 2, "Pin Description and

Configuration", Table 2-3, “Serial

Management Interface (SMI) Pins”

• Added pull-up to MDIO buffer type description

• Changed “VIS/VOD8 (PU)” to “VIS/VO8 (PU)”

Section 3.1.2.9, "100M Receive Data

Across the RMII Interface"

Updated description

Section 3.3, "HP Auto-MDIX Support"

Changed “100BASE-T” to “100BASE-TX”

Section 3.4.1.1, "CRS_DV - Carrier

Sense/Receive Data Valid"

Changed “100BASE-X” to “100BASE-TX”

Section 3.5, "Serial Management

Interface (SMI)"

Removed sentence stating “Non-supported registers

(such as 7 to 15) will be read as hexadecimal

“FFFF”.

Section 3.7.4.2, "REF_CLK Out Mode" Added note: “In REF_CLK Out Mode, REFCLKO will

not output when the device is in Energy Detect

Power-Down Mode or General Power-Down Mode.”

Section 3.8.3.1, "General Power-Down" Added note: “In REF_CLK Out Mode, REFCLKO will

not output when the device is in General Power-

Down Mode.”

Section 3.8.3.2, "Energy Detect Power-

Down (EDPD)"

Added note: “In REF_CLK Out Mode, REFCLKO will

not output when the device is in Energy Detect

Power-Down Mode.”

Section 3.8.9, "Cable Diagnostics"

Updated section with additional operation details

Chapter 4, "Register Descriptions"

Removed

- TDR Channel Threshold Maximum Register

- TDR Wait Counter Threshold Register

- TDR TX Pattern Generator Divider Register

Section 4.2.2, "Basic Status Register"

Updated definitions of bits 10:8

Section 4.2.18, "Special Control/Status

Indications Register"

Updated bit 11 definition

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