MSP430F423IPM datasheet(29/59 Pages) TI1

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SLAS421B – APRIL 2004 – REVISED NOVEMBER 2016

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Detailed Description

(1)

A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h

−01FFh) or from

within unused address ranges (0600h–0BFFh).

(2)

Multiple source flags

(3)

(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4)

Interrupt flags are in the module.

6.4

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-3 lists

the interrupt sources, flags, and vectors.

Table 6-3. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD

ADDRESS

PRIORITY

Power up

External reset

Watchdog

Flash memory

PC out of range(1)

WDTIFG

KEYV(2)

Reset

0FFFEh

15, highest

NMI oscillator fault

Flash memory access violation

NMIIFG(2)

OFIFG(2)

ACCVIFG(2)

(Non)maskable(3)

(Non)maskable

0FFFCh

0FFFAh

SD16

SD16CCTLx SD16OVIFG,

SD16CCTLx SD16IFG(2)(4)

Maskable

0FFF8h

0FFF6h

Watchdog timer

WDTIFG

Maskable

0FFF4h

USART0 receive

URXIFG0

Maskable

0FFF2h

USART0 transmit

UTXIFG0

Maskable

0FFF0h

0FFEEh

Timer_A3

TACCR0 CCIFG(4)

Maskable

0FFECh

Timer_A3

TACCR1 and TACCR2

CCIFGs, and TACTL TAIFG (2)(4)

Maskable

0FFEAh

I/O port P1 (8 flags)

P1IFG.0 to P1IFG.7(2)(4)

Maskable

0FFE8h

0FFE6h

0FFE4h

I/O port P2 (8 flags)

P2IFG.0 to P2IFG.7(2)(4)

Maskable

0FFE2h

Basic Timer1

BTIFG

Maskable

0FFE0h

0, lowest

MSP430F423IPM Datasheet(PDF) 29 Page - Texas Instruments

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