MSP430F423IPM datasheet(32/59 Pages) TI1

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MSP430F427, MSP430F425, MSP430F423

SLAS421B – APRIL 2004 – REVISED NOVEMBER 2016

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Detailed Description

6.6

Memory Organization

Table 6-9 summarizes the memory map of the MSP430F42x MCUs.

Table 6-9. Memory Organization

MSP430F423

MSP430F425

MSP430F427

Memory

Size

8KB

16KB

32KB

Interrupt vector

Flash

0FFFFh–0FFE0h

Code memory

Flash

0FFFFh–0E000h

0FFFFh–0C000h

0FFFFh–08000h

Information memory

Size

256 Byte

010FFh–01000h

Boot memory

Size

1KB

0FFFh–0C00h

RAM

Size

256 Byte

512 Byte

1KB

02FFh–0200h

03FFh–0200h

05FFh–0200h

Peripherals

16-bit

01FFh–0100h

8-bit

0FFh–010h

8-bit SFR

0Fh–00h

6.7

Bootloader (BSL)

The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU

memory through the BSL is protected by user-defined password. For complete description of the features

of the BSL and its implementation, see MSP430 Programming WIth the Bootloader (BSL).

BSL FUNCTION

PM PACKAGE PINS

Data transmit

53 - P1.0

Data receiver

52 - P1.1

6.8

Flash Memory

The flash memory (see Figure 6-7) can be programmed using the JTAG port, the bootloader, or in system

by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of

the flash memory include:

•

Flash memory has n segments of main memory and two segments of information memory (A and B) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

•

Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B

are also called information memory.

•

New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory before the first use.

MSP430F423IPM Datasheet(PDF) 32 Page - Texas Instruments

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