MSP430F423IPM datasheet(12/59 Pages) TI1

12 / 59 page

MSP430F427, MSP430F425, MSP430F423

SLAS421B – APRIL 2004 – REVISED NOVEMBER 2016

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Specifications

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

5.5

Thermal Resistance Characteristics, PM Package (LQFP64)

PARAMETER

VALUE

UNIT

RθJA

Junction-to-ambient thermal resistance, still air(1)

55.7

°C/W

RθJC(TOP)

Junction-to-case (top) thermal resistance(2)

16.7

°C/W

RθJB

Junction-to-board thermal resistance(3)

27.1

°C/W

ΨJB

Junction-to-board thermal characterization parameter

26.8

°C/W

ΨJT

Junction-to-top thermal characterization parameter

0.8

°C/W

5.6

Schmitt-Trigger Inputs

− Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS,

TDI/TCLK,TDO/TDI)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

VCC

MIN

MAX

UNIT

VIT+

Positive-going input threshold voltage

3 V

1.5

1.98

VIT-

Negative-going input threshold voltage

3 V

0.9

1.3

Vhys

Input voltage hysteresis (VIT+ - VIT- )

3 V

0.45

(1)

The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals

shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles.

5.7

Inputs P1.x, P2.x, TAx

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, external trigger signal

for the interrupt flag(1)

3 V

1.5

cycle

t(cap)

Timer_A capture timing

TAx

3 V

f(TAext)

Timer_A clock frequency externally

applied to pin

TAxCLK, INCLK t(H) = t(L)

3 V

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

3 V

MHz

(1)

The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.

(2)

The port pin must be selected as input.

5.8

Leakage Current

− Ports (P1 and P2)

(1)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

Ilkg(P1.x)

Leakage current, Port P1.x

Port 1: V(P1.x)

(2)

3 V

±50

Ilkg(P2.x)

Leakage current, Port P2.x

Port 2: V(P2.x)

(2)

3 V

±50

MSP430F423IPM Datasheet(PDF) 12 Page - Texas Instruments

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