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MSP430F423IPM Datasheet(PDF) 33 Page - Texas Instruments

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Part # MSP430F423IPM
Description  Mixed-Signal Microcontrollers
PDF  59 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430F423IPM Datasheet(HTML) 33 Page - Texas Instruments

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Segment 0
With Interrupt Vectors
Segment 1
Segment 2
Segment n−1
Segment n
32KB
Segment A
Segment B
Main Memory
Information Memory
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
08400h
083FFh
08200h
081FFh
01000h
010FFh
08000h
01080h
0107Fh
16KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
01000h
010FFh
0C000h
01080h
0107Fh
8KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0E400h
0E3FFh
0E200h
0E1FFh
01000h
010FFh
0E000h
01080h
0107Fh
33
MSP430F427, MSP430F425, MSP430F423
www.ti.com
SLAS421B – APRIL 2004 – REVISED NOVEMBER 2016
Submit Documentation Feedback
Product Folder Links: MSP430F427 MSP430F425 MSP430F423
Detailed Description
Copyright © 2004–2016, Texas Instruments Incorporated
Figure 6-7. Flash Memory Map
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430x4xx Family User's
Guide.
6.9.1
Oscillator and System Clock
The clock system is supported by the FLL+ module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+
clock module is designed to meet the requirements of both low system cost and low power consumption.
The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital
modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The
internal DCO provides a fast turnon clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
•
Main clock (MCLK), the system clock used by the CPU
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
•
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8



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