Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

WM8255 Datasheet(PDF) 37 Page - Cirrus Logic

Part # WM8255
Description  Single Channel 16-bit CIS/CCD AFE with RGB LED Current Drive
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8255 Datasheet(HTML) 37 Page - Cirrus Logic

Back Button WM8255 Datasheet HTML 33Page - Cirrus Logic WM8255 Datasheet HTML 34Page - Cirrus Logic WM8255 Datasheet HTML 35Page - Cirrus Logic WM8255 Datasheet HTML 36Page - Cirrus Logic WM8255 Datasheet HTML 37Page - Cirrus Logic WM8255 Datasheet HTML 38Page - Cirrus Logic WM8255 Datasheet HTML 39Page - Cirrus Logic WM8255 Datasheet HTML 40Page - Cirrus Logic WM8255 Datasheet HTML 41Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 37 / 49 page
background image
WM8255
Production Data
w
PD, Rev 4.7, August 2013
37
POWER ON SEQUENCE
In order to guarantee correct operation, the digital supply (DVDD) and analogue supply (AVDD1)
should be applied as specified in Figure 29 and Table 5.
If it is not possible to apply the recommended power up sequence, the user must wait until both
DVDD and AVDD1 have risen fully, then disable and enable the WM8255 by software write to EN
(R0, b0). It is then possible to apply further register writes and operate the WM8255 correctly.
When powering down the WM8255, no specific power down sequence is required.
REDUCED POWER
With DVDD applied, AVDD1 may be powered down with no loss to digital configuration data. This will
reduce the power consumption of the device whilst still keeping register settings and configurations.
Figure 29 Power On Sequence
Test Conditions
AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DVDD set up time to AVDD1 rising
edge
tPSU
100
μs
Table 5 Power On Timing
OPERATING MODES
Table 6 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
TIMING
REQUIREMENTS
REGISTER
CONTENTS WITH
CDS
REGISTER
CONTENTS
WITHOUT CDS
1
Monochrome/
Colour Line-by-Line
Yes
6 MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
2n:1 n
 2
SetReg1: 0F(hex)
SetReg1: 0D(hex)
2
Fast Monochrome/
Colour Line-by-Line
Yes
8 MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
3:1
Identical to Mode
1 plus SetReg3:
bits 5:4 must be
set to 0(hex)
Identical to
Mode 1
3
Maximum speed
Monochrome/
Colour Line-by-Line
No
12 MSPS
MCLK max = 24MHz
MCLK:VSMP ratio is
2:1
CDS not possible
SetReg1: 4D(hex)
Table 6 WM8255 Operating Modes
*Note: Maximum sample rate depends on the MCLK to VSMP ratio. A higher ratio will mean a lower
maximum sample rate for a specified MCLK speed.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com