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WM8255 Datasheet(PDF) 37 Page - Cirrus Logic |
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WM8255 Datasheet(HTML) 37 Page - Cirrus Logic |
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37 / 49 page ![]() WM8255 Production Data w PD, Rev 4.7, August 2013 37 POWER ON SEQUENCE In order to guarantee correct operation, the digital supply (DVDD) and analogue supply (AVDD1) should be applied as specified in Figure 29 and Table 5. If it is not possible to apply the recommended power up sequence, the user must wait until both DVDD and AVDD1 have risen fully, then disable and enable the WM8255 by software write to EN (R0, b0). It is then possible to apply further register writes and operate the WM8255 correctly. When powering down the WM8255, no specific power down sequence is required. REDUCED POWER With DVDD applied, AVDD1 may be powered down with no loss to digital configuration data. This will reduce the power consumption of the device whilst still keeping register settings and configurations. Figure 29 Power On Sequence Test Conditions AVDD1 = 5.75V, DVDD = 3.3V, AGND = DGND = AVDD2 = 0V, TA = 25C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DVDD set up time to AVDD1 rising edge tPSU 100 μs Table 5 Power On Timing OPERATING MODES Table 6 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE TIMING REQUIREMENTS REGISTER CONTENTS WITH CDS REGISTER CONTENTS WITHOUT CDS 1 Monochrome/ Colour Line-by-Line Yes 6 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 2n:1 n 2 SetReg1: 0F(hex) SetReg1: 0D(hex) 2 Fast Monochrome/ Colour Line-by-Line Yes 8 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 3:1 Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to Mode 1 3 Maximum speed Monochrome/ Colour Line-by-Line No 12 MSPS MCLK max = 24MHz MCLK:VSMP ratio is 2:1 CDS not possible SetReg1: 4D(hex) Table 6 WM8255 Operating Modes *Note: Maximum sample rate depends on the MCLK to VSMP ratio. A higher ratio will mean a lower maximum sample rate for a specified MCLK speed. |
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