AD7771BCPZ datasheet(44/99 Pages) AD

44 / 99 page

Data Sheet

AD7771

Rev. 0 | Page 43 of 98

Pins section for more information on how to generate a pulse in

the pin).

The phase offset register is multiplied internally by a factor that

depends on the decimation rate, as shown in Table 16.

Table 16. Phase Adjustment vs. Decimation Rate

Phase Adjustment Compensation

Decimation Rate

×1

≤255

×2

≤511

×4

≤1023

×8

≤2047

×16

≤4095

The maximum phase delay cannot be equal to or greater than

the decimation rate. If this is the case, the value changes

internally to the decimation rate value minus 1.

As an example, the phase mismatch between Channel 0 and

Channel 1 is 5°, and the ODR is 5 kSPS in high resolution mode. In

this case, the decimation rate is 2048 kHz/5 kHz = 409.6, which

means that the offset register value is multiplied internally by 2.

Assuming an input signal of 50 Hz, the number of MOD_

MCLK pulses required to sample a full period is 2048 kHz/

50 Hz = 40960 > 360°/40960 = 0.00878°.

If a 5° delay is required, the number of MOD_MCLK delays

must be 569 (5°/0.00878°) because the offset register is multiplied

by 2; the final offset register value is 409.6/2 − 569/2, which

gives a negative value. In this case, if the offset value programmed

to the register is higher than 204 (for example, 210 × 2 = 420),

the value is internally changed to 408, resulting in a phase

compensation of 408 × 0.00878° = 3.58°.

PGA Gain

The PGA gain can be selected individually by appropriately select-

ing Bits[7:6] in the CHx_CONFIG register, as shown in Table 17.

Table 17. PGA Gain Settings via CHx_CONFIG

CHx_CONFIG, Bits[7:6] Setting

PGA Gain Setting

×1

×2

×4

×8

If the Σ-Δ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference.

Decimation

The decimation defines the sampling frequency as follows:

•

In high resolution mode, the sampling frequency = MCLK/

(4 × decimation)

•

In low power mode, the sampling frequency = MCLK/

(8 × decimation)

Refer to the Sample Rate Converter (SRC) section for more

information.

GPIOx Pins

If the AD7771 operates in SPI control mode, the mode pins

operate as GPIOx pins, as shown in Figure 116. The GPIOx pins

can be configured as inputs or outputs in any order.

MAP

GPIO0

GPIO1

GPIO2

Figure 116. GPIOx Pin Functionality

Configuration control and readback of the GPIOx pins are set

via Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output)

and the GPIO_DATA register. Among other uses, the GPIOs

can control an external mux connected to the auxiliary inputs of

the SAR ADC. Use this mux to verify the results on the Σ-Δ ADCs.

In addition, the GPIOx pins can be used to externally trigger a

new decimation rate. Refer to the Sample Rate Converter (SRC)

section for more information about this functionality.

Σ-Δ Reference Configuration

The AD7771 can operate with internal or external references. In

addition, for diagnostic purposes, the analog supply can be used

as a reference, as shown in Table 18. REFx−/REFx+ allow the

selection of a voltage reference where the REFx+ voltage is

lower than the voltage on the REFx− pin.

Table 18. Σ-Δ References

Setting for

ADC_MUX_CONFIG,

Bits[7:6]

Channel 0 to

Channel 3

Channel 4 to

Channel 7

REF1+/REF1−

REF2+/REF2−

Internal reference

AVDD1A/AVSS1A

AVDD1B/AVSS1B

REF1−/REF1+

REF2−/REF2+

Reference buffer operation is described in Table 19. The selected

reference and buffer operation mode affect all channels.

If the Σ-Δ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference.

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