AD7771BCPZ datasheet(55/99 Pages) AD

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AD7771

Data Sheet

Rev. 0 | Page 54 of 98

SAMPLE RATE CONVERTER (SRC) (SPI CONTROL

MODE)

The AD7771 implements a patented featured called the SRC on

each Σ-Δ channel that allows the user to configure the output

data rate or sampling frequency to any desired value, including

noninteger values. The SRC achieves fine resolution control

over the Σ-Δ ADC ODR, up to 15.2 µSPS. In applications where

the ODR must change based on changes in the input signal to

maintain sampling coherency, the SRC provides fine control

over the ODR. For example, to achieve the highest classification

standard, Class A, in power quality applications, coherency

must be maintained for 0.01 Hz changes in the input power

line. Use the SRC to achieve this sampling frequency accuracy.

In pin control mode, the ODR is fixed per the predefined pin

control options. Consequently, a noninteger number cannot be

selected, as shown in Table 13.

To set the ODR, the user must program up to four registers,

depending on the decimation value: two registers to program the

integer value, N (the effective decimation rate), and two registers

to program the decimal value, the interpolation factor (IF).

The integer value registers are SRC_N_MSB, Bits[3:0] and

SRC_N_LSB, Bits[7:0]. The decimal part value registers are

SRC_IF_MSB, Bits[7:0] and SRC_IF_LSB, Bits[7:0].

As an example, if an output data rate of 2.8 kHz is required, the

decimation rate equates to

•

High resolution mode = 2048/2.8 = 731.428

•

Low power mode = 512/2.8 = 182.857

The register values for high resolution mode are as follows:

•

731 (decimal) = 0x2DB

•

SRC_N_MSB, Bits[3:0] = 0x02

•

SRC_N_LSB, Bits[7:0] = 0xDB

•

0.428 (decimal) = 0.428 × 216 = 28049 (decimal) = 0x6D91

•

SRC_IF_MSB, Bits[7:0] = 0x6D

•

SRC_IF_LSB, Bits[7:0] = 0x91

The SRC resolution depends on the decimal number used in the

decimation, as well as the modulator clock (MOD_MCLK), as

follows:

DEC

MOD

Resolution

MCLK

where:

MODMCLK is the modulator frequency.

DEC is the decimal portion of the decimation rate.

In high resolution mode, for a decimal decimation of 450, the

resolution is defined as

SPS

450

2048

–

The ODR can be updated on the fly, but a new ODR is effective

in three conversion cycles of the Σ-Δ ADCs. This condition

guarantees a smooth transition with no conversion results out

of range.

There are two different ways to change the ODR after a new

value is written in the SRC registers: via software or via

hardware, depending on the SRC_LOAD_SOURCE bit

(SRC_UPDATE register, Bit 7).

If the SRC_LOAD_SOURCE bit is clear, the new ODR value is

updated by setting the SRC_LOAD_UPDATE bit to 1. This bit

must be held high for at least two MLCK periods; return the bit

to 0 before attempting another update.

If SRC_LOAD_SOURCE is set, the GPIO0 pin controls the ODR

update externally. Apply a pulse in the GPIO2 pin, which is then

internally synchronized with the external MCLK clock, and the

resultant synchronous signal is output on the GPIO1 pin.

The GPIO1 and GPIO0 pins must be externally connected.

If multiple AD7771 devices must be synchronized, the GPIO1 pin

of one device can be connected to multiple devices. This synchro-

nization method requires the use of a common MCLK signal for all

the AD7771 devices connected, as shown in Figure 125.

GPIO2

GPIO0

MCLK

GPIO1

GPIO2

MCLK

GPIO1

GPIO2

MCLK

GPIO1

AD7771

SYNCHRONIZATION

LOGIC

PULSE

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MCLK

Figure 125. Hardware ODR Update

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