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AD7771BCPZ Datasheet(PDF) 86 Page - Analog Devices |
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AD7771BCPZ Datasheet(HTML) 86 Page - Analog Devices |
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86 / 99 page  Data Sheet AD7771 Rev. 0 | Page 85 of 98 CHANNEL 6 GAIN MIDDLE BYTE REGISTER Address: 0x044, Reset: 0x00, Name: CH6_GAIN_MID_BYTE Com bined gain regis ter Channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH6_GAIN_ALL[15:8] (R/W) Table 111. Bit Descriptions for CH6_GAIN_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_GAIN_ALL[15:8] Combined Gain Register Channel 6 0x0 R/W CHANNEL 6 GAIN LOWER BYTE REGISTER Address: 0x045, Reset: 0x00, Name: CH6_GAIN_LOWER_BYTE Com bined gain regis ter Channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH6_GAIN_ALL[7:0] (R/W) Table 112. Bit Descriptions for CH6_GAIN_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH6_GAIN_ALL[7:0] Combined Gain Register Channel 6 0x0 R/W CHANNEL 7 OFFSET UPPER BYTE REGISTER Address: 0x046, Reset: 0x00, Name: CH7_OFFSET_UPPER_BYTE Com bined offs et regis ter Channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH7_OFFSET_ALL[23:16] (R/W) Table 113. Bit Descriptions for CH7_OFFSET_UPPER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[23:16] Combined Offset Register Channel 7 0x0 R/W CHANNEL 7 OFFSET MIDDLE BYTE REGISTER Address: 0x047, Reset: 0x00, Name: CH7_OFFSET_MID_BYTE Com bined offs et regis ter Channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH7_OFFSET_ALL[15:8] (R/W) Table 114. Bit Descriptions for CH7_OFFSET_MID_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[15:8] Combined Offset Register Channel 7 0x0 R/W CHANNEL 7 OFFSET LOWER BYTE REGISTER Address: 0x048, Reset: 0x00, Name: CH7_OFFSET_LOWER_BYTE Com bined offs et regis ter Channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] CH7_OFFSET_ALL[7:0] (R/W) Table 115. Bit Descriptions for CH7_OFFSET_LOWER_BYTE Bits Bit Name Settings Description Reset Access [7:0] CH7_OFFSET_ALL[7:0] Combined Offset Register Channel 7 0x0 R/W |
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