AD7771BCPZ datasheet(72/99 Pages) AD

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Data Sheet

AD7771

Rev. 0 | Page 71 of 98

GENERAL USER CONFIGURATION 1 REGISTER

Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1

If all SD channels are disabled, setting

this bit high allows DCLK to continue

toggling

Soft Res et

11: 1st write.

10: 2nd write.

01: No Effect.

00: No Effect.

Power Mode

1: High Resolution.

0: Low Power (1/4)

Power-Down signal for internal oscillator.

Active Low

Power-Down VCM Buffer. Active Low

Power-Down SAR. Active Low

Power-Down Internal Reference Output

Buffer. Active Low

[7] ALL_CH_DIS_MCLK_EN (R/W)

[1:0] SOFT_RESET (R/W)

[6] POWERMODE (R/W)

[2] PDB_RC_OSC (R/W)

[5] PDB_VCM (R/W)

[3] PDB_SAR (R/W)

[4] PDB_REFOUT_BUF (R/W)

Table 61. Bit Descriptions for GENERAL_USER_CONFIG_1

Bits

Bit Name

Settings

Description

Reset

Access

ALL_CH_DIS_MCLK_EN

If all Σ-Δ channels are disabled, setting this bit high allows DCLK to

continue toggling.

0x0

R/W

POWERMODE

Power Mode.

0x0

R/W

Low power (1/4).

High resolution.

PDB_VCM

Power-Down VCM Buffer. Active low.

0x1

R/W

PDB_REFOUT_BUF

Power-Down Internal Reference Output Buffer. Active low.

0x0

R/W

PDB_SAR

Power-Down SAR. Active low.

0x0

R/W

PDB_RC_OSC

Power-Down Signal for Internal Oscillator. Active low.

0x1

R/W

[1:0]

SOFT_RESET

Soft Reset

0x0

R/W

No effect

2nd write

1st write

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