AD7771BCPZ datasheet(45/99 Pages) AD

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AD7771

Data Sheet

Rev. 0 | Page 44 of 98

Table 19. Reference Buffer Operation Modes

Reference Buffer

Operation Mode

REFx+

REFx−

Enabled

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0

Precharged

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1

Disabled

BUFFER_CONFIG_1, Bit 4 = 0

BUFFER_CONFIG_1, Bit 3 = 0

Table 20. Additional Disable Power-Down Blocks

Block

Notes

VCM

GENERAL_USER_CONFIG_1, Bit 5

Enabled by default

Reference Buffer

BUFFER_CONFIG_1, Bits[4:3]

Precharge mode by default

Internal Reference Buffer

GENERAL_USER_CONFIG_1, Bit 4

Disabled by default

Σ-Δ Channel

CH_DISABLE, Bits[7:0]

All channels enabled

SAR

GENERAL_USER_CONFIG_1, Bit 3

Disabled by default

Internal Oscillator

GENERAL_USER_CONFIG_1, Bit 2

Enabled by default

Power Modes

The AD7771 offers different power modes to improve the

power efficiency, high resolution and low power mode, which

can be controlled via GENERAL_USER_CONFIG_1, Bit 6. To

further reduce the power, additional blocks can be disabled

independently, as described in Table 20.

If the power mode changes, a pulse on the SYNC_IN pin is

required.

Sinc3 and Sinc5 Filters

The AD7771 implements sinc3 and sinc5 digital filters. By

default, the device powers up with the sinc3 filter, but it can be

changed by setting GENERAL_USER_CONFIG_2, Bit 6. If the

sinc filter is changed, a pulse in the SYNC_IN pin is required.

LDO Bypassing

The internal LDOs can be individually bypassed and an external

supply can be applied directly to the AREG1CAP, AREG2CAP,

or DREGCAP pin. Table 21 shows the absolute minimum and

maximum supplies for these pins, as well as the associated

Table 21. LDO Bypassing

LDO

BUFFER_CONFIG_2,

Bits[2:0]1

Supply

Max (V)

Min (V)

AREG1CAP

1XX

1.9

1.85

AREG2CAP

X1X

1.9

1.85

DREGCAP

XX1

1.9

1.65

X means don’t care.

DIGITAL SPI

The SPI serial interface on the AD7771 consists of four signals:

CS, SDI, SCLK, and SDO. A typical connection diagram of the

SPI is shown in Figure 117.

DSP/FPGA

AD7771

SCLK

SDI

SDO

Figure 117. SPI Control Interface—AD7771 is the SPI Slave, Digital Signal

Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master

The SPIs operates in Mode 0 and Mode 3, CPOL = 0, CPHA = 0

(Mode 0) or CPOL = 1, CPHA = 1 (Mode 3).

In pin control mode, the SDI can read back the Σ-Δ results,

depending on the level of the CONVST_SAR pin, as described in

Table 13.

In SPI control mode, the SPI transfers data into the on-chip

registers while the SDO pin reads back data from the on-chip

registers or reads the SAR or the Σ-Δ conversions results,

depending on the selected operation mode.

The SDO data source in SPI control mode is defined by the

GENERAL_USER_CONFIG_2 and GENERAL_USER_

CONFIG_3 registers, as described in Table 22.

Table 22. SPI Operation Mode in SPI Control Mode

GENERAL_USER_

CONFIG_2, Bit 5

Setting

GENERAL_USER_

CONFIG_3, Bit 4

Setting1

Mode

Internal register

Σ-Δ data conversion

SAR conversion

X means don’t care.

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