TSB41BA3APFP datasheet(48/66 Pages) TI

48 / 66 page

TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

interface reset and disable (continued)

PCLK

(a)

(c)

(b)

CTL0, CTL1

D0 − D7

LREQ

LPS

TLPS_RESET

(d)

TLPS_DISABLE

Figure 20. Interface Disable

The sequence of events for disabling the PHY-LLC is as follows:

(a) Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

(d) Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, then the PHY terminates PCLK

activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state.

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization.

TSB41BA3APFP Datasheet(PDF) 48 Page - Texas Instruments