TSB41BA3APFP datasheet(59/66 Pages) TI

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TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

receive (continued)

The sequence of events for a null packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a

status transfer operation that is in progress so that the CTL lines may change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

The PHY asserts at least one idle cycle following a receive operation.

Table 36. Receive Speed Codes and Format

D0−D7

DATA RATE AND FORMAT

0000 0000

S100 legacy

0000 0001

S100 beta

0000 0100

S200 legacy

0000 0101

S200 beta

0000 1000

S400 legacy

0000 1001

S400 beta

0000 1101

S800 beta

1111 1111

Data-on indication

All Others

Reserved

NOTE: Y = Output as 1 by PHY, ignored by LLC.

X = Output as 0 by PHY, ignored by LLC.

transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.

If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals and the grant type on the D terminals for one PCLK cycle, followed

by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (11b) or

transmit (01b) on the CTL terminals. If the PHY does not detect a hold or transmit state within eight PCLK cycles,

then the PHY takes control of the PHY-link interface. The hold state is used by the LLC to retain control of the

bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the

LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0.

The PHY asserts data-prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle. If the hold is

asserted, then the hold is immediately followed by one clock cycle of idle. The link then releases the PHY-link

interface by putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the

PHY-link interface.

TSB41BA3APFP Datasheet(PDF) 59 Page - Texas Instruments

TSB41BA3APFP Datasheet(HTML) 59 Page - Texas Instruments

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