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windings affects the transformer (the aux winding level

does not properly collapse in presence of an output

short). Here, every time the internal 0.8 V maximum

peak current limit is activated, an error flag, IpFlag, is

asserted and a time period starts, thanks to an adjustable

timer. If the timer reaches completion while the error

flag is still present, the controller stops the pulses and

goes into a latch−off phase, operating in a

low−frequency burst−mode. To limit the fault output

power, a divide−by−two circuitry is installed on the

VCC pin and requires twice a start−up sequence before

another attempt to re−start is. As soon as the fault

disappears, the SMPS resumes operation. The latch−off

phase can also be initiated, more classically, when VCC

drops below VCC(min) (7.9 V typical).

Start−up Sequence

When the power supply is first connected to the mains

outlet, the internal current source is biased and charges up

the VCC capacitor. When the voltage on this VCC capacitor

reaches the VCC(on) level (typically 15 V), the current source

turns off, reducing the amount of power being dissipated. At

this time, the VCC capacitor only supplies the controller, and

the auxiliary supply should take over before VCC collapses

below VCC(min). Figure 32 shows the internal arrangement

of this structure:

Figure 32. The Current Source Brings VCC Above

15 V (typical) and then Turns Off

IC1 or 0

VCC(on)

VCClatch

In some fault situations, a short−circuit can purposely

occur between VCC and ground. In high line conditions

(VHV = 370 Vdc) the current delivered by the startup device

will seriously increase the junction temperature. For

instance, since IC1 equals 2 mA (the min corresponds to the

highest TJ), the device would dissipate 370 x 2m = 740 mW.

To avoid this situation, the controller includes a novel

circuitry made of two startup levels, IC1 and IC2. At

power−up, as long as VCC is below a certain level (1.8 V

typ.), the source delivers IC1 (around 500

mA typical), then,

when VCC reaches 1.8 V, the source smoothly transitions to

IC2 and delivers its nominal value. As a result, in case of

short−circuit between VCC and GND, the power dissipation

will drop to 370 x 500

m = 185 mW. Figure 33 portrays this

particular behaviour:

Vth

IC1 min

IC2 min

Figure 33. The Startup Source Now Features a

Dual−level Startup Current

CVCC = 33 mF

VCC(on)

VCC

The first startup period is calculated by the formula C x V

= I x t, which implies a 22

m x 1.8 / 200 m = 198 ms startup

time for the first sequence. The second sequence is obtained

by changing to 2 mA with a delta V of VCC(on) – VTh = 15

– 1.8 = 13.2 V, which finally leads to a second startup time

of 13.2 x 22

m / 2m = 145 ms. The total startup time becomes

198 m + 140 m = 343 ms with a worst case condition on the

startup source only. Please note that this calculation is

approximated by the presence of the knee in the vicinity of

the transition.

As soon as VCC reaches VCC(on), drive pulses are

delivered on pin 9 and the auxiliary winding increases the

voltage on the VCC pin. Because the output voltage is below

the target (the SMPS is starting up), the controller smoothly

ramps up the peak current to Ip,max (0.8 V / Rsense) which is

reached after a typical soft−start period. This soft−start

period is internally fixed and lasts typically 5 ms. As soon

as the peak current setpoint reaches its maximum (during the

startup period but also anytime an overload occurs), an

internal error flag is asserted, Ipflag, indicating that the

system has reached its maximum current limit set point (Ip

= Ip,max). As soon as the error flag gets asserted, the current

source on pin 3 is activated and charges up the capacitor

connected to this pin. If the error flag is still asserted when

the timer capacitor has reached the threshold level

VtimFault, (which is about 100 ms with a 0.22 mF typically),

then the controller assumes that the power supply has really

undergone a fault condition and immediately stops all pulses

to enter a safe burst operation. Figure 34 depicts the VCC

evolution during a proper startup sequence, showing the

state of the internal error flag:

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