DAP018A/B/C/D/F

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15

SS = 5 ms

Current

setpoint

IpFlag

100ms

Timer

Full power

Freq. foldback / skip level

regulation

No error has

been confirmed

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Feedback loops

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Figure 34. An Error Flag gets Asserted

VCC(on)

VCC(min)

VCC

VFB

Ip,max

VCClatch

VCCreset

An error flag gets asserted as soon as the current setpoint reaches its upper limit (0.8 V/Rsense). Here the timer lasts 100 ms,

a 0.22

mF capacitor being connected to pin 3.

Short−circuit or Overload Mode

There can be various events that force a fault on the

primary side controller. We can split them in different

situation, each having a particular configuration:

1. the converter regulates but the auxiliary winding

collapses: this is a typical situation linked to the

usage of a constant−current / constant−voltage

(CC−CV) type of secondary−side controller. If the

output current increases, the voltage feedback loop

gives up and the current loop takes over. It means

that Vout goes low but the feedback loop is still

closed because of the output current monitoring.

Therefore, seen from the primary side, there is no

fault. However, there are numerous charger

applications where the output voltage shall not go

below a certain limit, even if the current is

controlled. To cope with this situation, the

controller features a precise under−voltage lockout

comparator biased to a VCC(min) level. When this

level is crossed, whatever the other pin conditions,

pulses are stopped and the controller enters the

safe hiccup mode, trying to re−start. Figure 35

shows how the converter will behave in this

situation. If the fault goes away, the SMPS

resumes operation.