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DAP018x Marking, DAP018DDR2G Datasheet(PDF) 22 Page - ON Semiconductor

Part # DAP018DDR2G
Description  PWM Current-Mode Controller for High-Power Universal Off-Line Supplies
PDF  28 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

DAP018DDR2G Datasheet(HTML) 22 Page - ON Semiconductor

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DAP018A/B/C/D/F
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22
BO
signal
restart
Mains interruption
The BO information is latched. The next re−start
Drv
Figure 45. A Brown−out Event Immediately Stops the Driving Pulses
occurs when VCC hits VCC(on) again
VBO(on)
VBO(off)
Controller waits for the next VCC(on) event (fresh re−start)
Vbulk
VCCreset
VCClatch
VCC(min)
VCC(on)
VCC
When the bulk comes back to its normal level, the
controller waits for the next VCC(on) event to re−start
pulsing. In this case, the BO re−appears while VCC was still
ok but the controller waits for VCC to ramp down to VCClatch
then performs a fresh re−start before pulsing again.
The bridge resistors can be evaluated using the following
equations:
Rupper +
VBO,on * VBO,off
IBO
(eq. 1)
Rlower +
VBORupper
VBO,off * VBO
(eq. 2)
Where VBO = 1 V typical and IBO = 10 mA typical.
Suppose the adapter designer needs a turn−on voltage of
100 Vdc and a turn−off voltage of 50 Vdc, then the upper
resistor would be 4.9 M
W and the lower side resistor 100 kW.
The total dissipation for a 330 Vdc bulk rail would amount
to 22 mW.
* Please note that the current source arrangement brings
un−precision to the turn−on voltage only, whereas the
turn−off voltage is only dependent on the VBO reference
voltage.
Frequency Foldback and Skip Cycle
Unlike its predecessor, Speedking II implements a
frequency reduction in low power mode. Also called
frequency foldback, this technique has proven to offer a
good performance, especially in the middle of the power
range. On this controller, the foldback occurs when the peak
current reaches a level set via the original skip pin (pin 5).
Once the peak current reaches this value, via a decrease in
the feedback voltage, the controller freezes it and the only
way to further reduce the output power is to fold the
frequency back. The frequency variation is ensured over a
delta feedback voltage of around 500 mV. When the
frequency hits the frequency limit (
Ftrans), the frequency
reduction is stopped. At this point, if the load goes further
down, the feedback voltage drops and when it reaches
300 mV, the controller enters traditional skip−cycle (no
soft−burst).
At full power, the peak current varies according to the
power demand, the switching frequency being fixed to
65 kHz. The feedback voltage is allowed to move between
300 mV and 3.4 V which is the upper feedback limit beyond
which a fault is detected. When the load starts to decrease,
the feedback voltage goes down to impose lower peak



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