DAP018x Marking, DAP018DDR2G datasheet(19/28 Pages) ONSEMI

19 / 28 page

DAP018A/B/C/D/F

http://onsemi.com

Figure 40. The Part is Reset when VCC Reaches 5 V or when BO

Senses the Bulk Capacitor Voltage is Back to Normal

The user has unplugged, reset!

Fault!

Vlatch

Drv

VCC(on)

VCC(min)

VCCreset

VCClatch

VCC(min)

VCC(on)

VCC

If for any reason the latch pin level grows above Vlatch, the

part immediately stops pulsing and stays latched in this

position until the user cycles down the power supply. The

reset actually occurs if VCC drops below 5 V, e.g. if the

adapter user disconnects it from the mains. Figure 40 details

the operating diagrams in case of a fault. Please note the

presence of RC time constant on the comparator output,

aimed to filtering any spurious oscillations linked to an

eventual noise presence. The typical value of this time

constant is 20

ms.

On both OVP and OTP events and in the case of a

latched−OCP version, the latch reset occurs in the following

conditions:

• a user reset via a mains interruption (unplug and replug

adapter) which is long enough to let the VCC capacitor

discharge to the controller reset level of 5 V.

• for B & D versions, a reset can occur if the brown−out

circuitry is asserted before the VCC reaches 5 V.

Soft−start

The Speedking II features an internal soft−start circuit

activated during the power on sequence (PON) but also in

fault recovery (short−circuit protection or brown−out

release). As soon as VCC reaches VCC(on), the peak current

is gradually increased from nearly zero up to the maximum

clamping level (e.g. 0.8 V/Rsense). The peak current is

clamped at 0.8 V/Rsense through the entire soft−start period

until the supply enters regulation. Figure 41 shows a typical

startup shot.

vss vcc

8.56m

9.23m

9.90m

10.6m

11.2m

−300m

100m

500m

900m

1.30

7.95m

8.95m

9.95m

10.9m

11.9m

time in seconds

9.00

10.0

11.0

12.0

13.0

vss vcc

−300m

100m

500m

900m

1.30

9.00

10.0

11.0

12.0

13.0

Figure 41. Soft−start is Activated During a Start−up Sequence, an

Auto−recovery Burst−mode or when the Brown−out Pin is Released

5 ms

VCC(on)

VCC

Ip(t)

DAP018x Marking, DAP018DDR2G Datasheet(PDF) 19 Page - ON Semiconductor

DAP018DDR2G Datasheet(HTML) 19 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL