DAP018A/B/C/D/F

http://onsemi.com

16

IpFlag

Timer

Drv

regulation

Duration given

by aux. cap.

Current loop

action keeps FB

OK (CC operation)

Can be very

slow...

< 100ms

< 100ms

Figure 35. First Fault Mode Case

VCC

VFB

VCClatch

VCCreset

VCC(on)

VCC(min)

First fault mode case, the auxiliary winding collapses but feedback is still there (0.22

mF timer capacitor)

2. In the second case, the converter operates in

regulation, but the output is severely overloaded.

However, due to the bad coupling between the

power and the auxiliary windings, the controller

VCC does not go low. The peak current is pushed

to the maximum and the timer starts to count.

Upon completion, all pulses are stopped and

dual−startup hiccup mode is entered. If the fault

goes away, the SMPS resumes operation.