DAP018A/B/C/D/F

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18

The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the VCC capacitor. Figure 38

details the various time portion a hiccup is made of:

Drv

timer

timer

Figure 38. The Burst Period is Ensured by the VCC Capacitor

Charge / Discharge Cycle (here a 0.22 mF capacitor on timer)

VCC

VCClatch

VCCreset

t1

t2

t′1

t3

t′2

VCC(on)

VCC(min)

If by design we have selected a 22

mF VCC capacitor, it

becomes easy to evaluate the burst period and its duty−cycle.

This can be done by properly identifying all time events on

Figure 38 and applying the classical formula:

t + CDV

I

• t1: I = ICC3 = 600 mA,

ΔV = 9 – 6.5 = 2.5 V ³ t1 = 91 ms

• t2: I = 3 mA, ΔV = 15 – 6.5 = 8.5 V ³ t1 = 62 ms

• t3: I = 600 mA, ΔV = 15 – 6.5 = 8.5 V ³ t1 = 311 ms

• t′1 = t1 = 91 ms

• t′2 = t2 = 62 ms

The total period duration is thus the sum of all these events

which leads to Tfault = 617 ms. If the timer lasts 100 ms, then

our duty−cycle in auto−recovery burst equals 100/(617 +

100)

≈ 13%, which is good. Should the user like to further

decrease or, to the contrary, increase this duty−cycle,

changing the VCC capacitor is an easy job.

Latch−off and Over Voltage Protection

Speedking II features a fast comparator that permanently

monitors pin 2 level. Figure 39 details how it is internally

arranged:

Figure 39. A Comparator Monitors Pin 2 and

Latches−off the Part in Case the Threshold is

Reached

Rupper

-

+

Rlower

10 nF

C1

2

Vlatch

+

VCCaux

+

20 ms

time

constant

aux.

S

R

Q

Q

Latched

Fault

5 V Reset