DAP018A/B/C/D/F

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25

65kHz

68.9kHz

61.1kHz

adjustable

Figure 50. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Jitter ramp

Internal

sawtooth

Over Power Protection

There are several known ways to implement Over Power

Protection (OPP), all suffering from particular problems.

These problems range from the added consumption burden

on the converter or the skip−cycle disturbance brought by

the current−sense offset. A way to reduce the power

capability at high line is described by Figure 52. On this

drawing, a voltage is derived from the auxiliary winding and

produces a negative level during the on−time of the main

power transistor. The negative voltage amplitude directly

relates to the input level via the transformer turn ratio linking

the primary winding to the auxiliary winding. Figure 51

depicts the typical signal obtained on the auxiliary winding:

1 v(24)

464u

472u

480u

488u

496u

time in seconds

−40.0

−20.0

0

20.0

40.0

1

1

−40.0

−20.0

0

20.0

40.0

1

Figure 51. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time

off−time

on−time

N1(Vout + Vf)

−N2Vbulk

During the off−time, the voltage plateaus to a positive

level depending on the turn ratio between the output winding

(Ns) and the power winding. This ratio is noted N1. During

the on−time, the transformer terminal swings to a negative

voltage whose amplitude now depends on the turn ratio N2,

equal to the primary (Np) to the auxiliary winding ratio

(Naux). If we place a resistive divider between the auxiliary

winding and the OPP pin, as suggested by Figure 52, we

have a means to influence the internal setpoint as the bulk

voltage increases. The equations to design the network are

fairly simple:

Suppose we need to reduce the peak current from 2.5 A at

low line, to 2 A at high line. This corresponds to 20%

reduction or a setpoint voltage of 640 mV. To reach this

level, then the negative voltage developed on the OPP pin

must reach:

VOPP + 800 * 640 + −160 mV

(eq. 4)