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currents. When the feedback pin reaches the Vfold level, the

peak current is set to Vfold /4.2 and cannot decrease

anymore. The feedback voltage continues to go down but it

now changes the switching frequency down to 26 kHz

(typical), naturally reducing the amount of transmitted

power. When the feedback touches a typical 300 mV limit,

skip−cycle takes place. The whole behavior is illustrated by

Figure 46:

Figure 46. The Controller Changes its Operating Frequency in Light Load Conditions

Further details are given by Figure 47 which represents

both switching frequency and peak current setpoints in

relationship to the feedback voltage. Pin 5 provides a means

to alter the foldback limit. To fine tune the efficiency but also

to combine a low skip current level and a reduced acoustic

noise in standby, the designer must wire a resistor to ground

to set the foldback level (Figure 48). As we internally have

a 10

mA current source, the relationship is straightforward:

Rfold +

Vfold

10 m

(eq. 3)

For instance, suppose we want to set the folback point to

1 V, then the resistor value should be 100 k

W. We

recommend to put a 10 nF capacitor to ground on this pin.

Both the resistor and the capacitor must be placed very close

to the controller to avoid any noise pick−up.

Because the clock frequency must reach 26 kHz at a

feedback voltage of 300 mV, pin 5 level cannot be set too low

in order to provide enough dynamic range for the

Voltage−Controlled Oscillator (VCO). To obtain a good

linearity, we recommend a minimum voltage dynamics of

300 mV, which implies a level on pin 5 always above

600 mV. Also, setting the frequency foldback too low will

alter the performance in standby power.

The graphs in Figure 47 (65 kHz version) depict the

operation in light load conditions where the frequency is

decreased down to 26 kHz (typical)

Figure 47. Operation in Light Load Conditions

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